參數(shù)資料
型號(hào)： IDT88P8342BHI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 25/98頁
文件大小： 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8342BHI
31
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
SPI-4 ingress interface configurable parameters:
The IDT88P8342 can interface to either a Link or a PHY layer device. The
SPI-4 port can be enabled or disabled.
TheSPI-4ingressbitsarealignedwiththeingressclock.Inaddition,theSPI-
4 words are then aligned among each other to produce valid words. This is
performed both on the data channel and the status channel. The bit alignment
algorithm runs as long as the interface is active. The word alignment algorithm
is run during training intervals.
SPI-4 ingress per-LID configurable parameters
SPI-4 to SPI-3 LID map
256 entries, one per SPI-4 LP
SPI-3 physical interface identifier
SPI-3 LID
Enable bit per LID
SPI-4 ingress packet length check
EachLIDontheSPI-4ingressinterfacehastheabilitytobeprogrammedfor
minimum and maximum packet length. The minimum packet length can be set
from 0 to 255 bytes in one byte increments. The maximum packet length can
be set from 0 to 16,383 bytes in one byte increments. Packets shorter or longer
thansetbytheseparameterswillbeoptionallycountedintheshortorlongpacket
counter for that LID.
SPI-3 egress configurable parameters
Length of SPI-3 packet fragment
All packet fragments from a particular SPI-3 physical interface are program-
mabletoanequallengthwiththepossibleexceptionofanEOPfragmentwhich
may be shorter.
SPI-3 egress poll length
Applies when the SPI-3 interface is acting as a Link layer device when using
the packet level polling mode
Causes polling of the PHY for the logical ports associated with LIDs ranging
from [0 up to POLL_LENGTH] to find logical ports that can accept data
Poll range is 0-63 LPs.
SPI-3 egress per-LID configurable parameters
Many parameters to control the flow of data are programmable per LID. The
following paragraphs describe these parameters.
SPI-3 egress LID to LP map
one map per SPI-3 physical port
64 entries per map, one per LID
LP enable bit per LP
Bit reversal enable per LP
SPI-3 egress multiple burst enable
Multiple Burst Enable allows more than one burst to be sent to an LP. This
featureisincludedtorelievesystemswithlonglatencybetweenupdates.When
this feature is not enabled, only one burst per LP is allowed into the round robin
SPI-3 egress buffers at a time.
SPI-4 ingress to SPI-3 egress data memory
SPI-3 egress control
There is a SPI-3 egress port descriptor table for the paths out of the data
memory. The function a SPI-3 egress port descriptor table is to define where
data goes after leaving the main data memory. There are three configurable
options:
SPI-3 egress
Microprocessor Interface Capture
Discard
Maximum number of memory segments
Defines the largest Buffer available to an LP / LID
Each segment is 256 bytes
Range 1 – 508 in increments of one segment
The figure below shows the datapath through the device from the SPI-4
interface to the SPI-3 interface.
Figure 19. SPI-4 ingress to SPI-3 egress datapath
…
JTAG
uproc
LID Counters Memory
2 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
Interface
Bloc
k
Chip Counters Memory
Interface
Bloc
k
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6371 drw13
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