參數(shù)資料
型號： IDT88P8342BHI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 60/98頁
文件大小： 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8342BHI
63
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Non critical LID associated capture table
(Block_base 0x0C00 + Register_offset 0x10-0x15)
The Non critical LID associated capture table is at Block_Base 0x0C00 +
Register_Offset 0x10-0x15. The Non critical LID associated capture table is
used to determine the EVENT_TYPE of SPI-3 and SPI-4 per-LID or per-LP
interrupts.TheEVENT_TYPEcodingisusedtoindicatewhicheventorevents
arepertinenttotheinterruptintheTable64-LIDassociatedinterruptindication
register(0x0E). The Non critical LID associated capture table is used to
determinetheEVENT,andmultiplebitscanbeactiveatthesametime.TheNon
critical LID associated capture table is read-only.
SPI-3 to SPI-4 critical LID interrupt indication
registers (Block_base 0x0C00 + Register_offset
0x16-0x17)
TheSPI-3toSPI-4criticalLIDinterruptindicationregistersareatBlock_Base
0x0C00 + Register_offset 0x16-0x17.
CriticaleventsarecapturedperLIDintheSPI-3toSPI-4criticalLIDinterrupt
indication registers. An interrupt is generated when enabled by the enable flag
intheSPI-3toSPI-4criticalLIDinterruptenableregisters.ASPI-3toSPI-4critical
LIDinterruptindicationregisterhasreadandwriteaccess.Aninterruptindication
isclearedbywritingalogicalonetotheappropriatebitofaSPI-3toSPI-4critical
LID interrupt indication register. Only one kind of critical event is defined-buffer
overflow. Each bit of the LID field set to logical one indicates the presence of a
buffer overflow event. A summary indication of as to which of the two sources,
SPI-3toSPI-4orSPI-4toSPI-3,isresponsibleforthecriticalinterruptisindicated
in the Table 71 Critical events source indication register (0x1E).
SPI-3 to SPI-4 critical LID interrupt enable regis-
ters (Block_base 0x0C00 + Register_offset 0x18-
0x19)
TABLE 66 - NON CRITICAL LID ASSOCIATED
CAPTURE TABLE (REGISTER_OFFSET 0x10-0x15)
Register
EVENT_TYPE
Associated
field
0x00
Inactive ingress SPI-3 logical port event
LP (8 bits)
0x01
SPI-3 ingress data parity error
LID (6 bits)
0x02
SPI-4 illegal SOP sequence event
LID (6 bits)
0x03
SPI-4 illegal EOP sequence event
LID (6 bits)
0x04
SPI-3 illegal SOP sequence event
LID (6 bits)
0x05
SPI-3 illegal EOP sequence event
LID (6 bits)
TABLE 67 - SPI-3 TO SPI-4 CRITICAL LID INTER-
RUPTINDICATIONREGISTERS
(REGISTER_OFFSET 0x16-0x17)
Register
Field
Bits
Length
Initial Value
0x16
LID[31:0]
31:0
32
0x00
0x17
LID[63:32]
31:0
32
0x00
TABLE68-SPI-3TOSPI-4CRITICALLIDINTERRUPT
ENABLE REGISTERS (REGISTER_OFFSET 0x18-
0x19)
Register
Field
Bits
Length
Initial Value
0x18
LID[31:0]
31:0
32
0x00
0x19
LID[63:32]
31:0
32
0x00
TheSPI-3toSPI-4criticalLIDinterruptenableregistershavereadandwrite
access. A SPI-3 to SPI-4 critical LID interrupt enable register bits enable the
corresponding bits in a SPI-3 to SPI-4 critical LID interrupt indication register.
SPI-4 to SPI-3 critical LID interrupt indication
registers (Block_base 0x0C00 + Register_offset
0x1A-0x1B)
TABLE69-SPI-4TOSPI-3CRITICALLIDINTERRUPT
INDICATIONREGISTERS(REGISTER_OFFSET
0x1A-0x1B)
Register
Field
Bits
Length
Initial Value
0x1A
LID[31:0]
31:0
32
0x00
0x1B
LID[63:32]
31:0
32
0x00
TheSPI-4toSPI-3criticalLIDinterruptindicationregistersareatBlock_Base
0x0C00 + Register_offset 0x1A-0x1B.
Critical events are captured per LID in a SPI-4 to SPI-3 critical LID interrupt
indication register. An interrupt is generated when enabled by the enable flag
in the SPI-4 to SPI-3 critical LID interrupt enable register. The SPI-4 to SPI-3
criticalLIDinterruptindicationregistershavereadandwriteaccess.Aninterrupt
indication is cleared by writing a logical one to the appropriate bit of a SPI-4 to
SPI-3 critical LID interrupt indication register. Only one kind of critical event is
defined-buffer overflow. Each bit of a LID field set to logical one indicates the
presence of a buffer overflow event. A summary indication of as to which of the
two sources, SPI-3 to SPI-4 or SPI-4 to SPI-3, is responsible for the critical
interrupt is indicated in the Table 71 Critical events source indication register
(0x1E).
SPI-4 to SPI-3 critical LID interrupt enable regis-
ters (Block_base 0x0C00 + Register_offset 0x1C-
0x1D)
TABLE 70 - SPI-4 TO SPI-3 CRITICAL LID INTER-
RUPTENABLEREGISTERS(REGISTER_OFFSET
0x1C-0x1D)
Register
Field
Bits
Length
Initial Value
0x1C
LID[31:0]
31:0
32
0x00
0x1D
LID[63:32]
31:0
32
0x00
TABLE 71 - CRITICAL EVENTS SOURCE INDICA-
TION REGISTER (REGISTER_OFFSET 0x1E)
Field
Bits
Length
Initial Value
SPI34_OVR
0
1
0b0
SPI43_OVR
1
0b0
Reserved
31:2
30
0x0
TheSPI-4toSPI-3criticalLIDinterruptenableregistershavereadandwrite
access. The SPI-4 to SPI-3 critical LID interrupt enable register bits enable the
correspondingbitsintheSPI-4toSPI-3criticalLIDinterruptindicationregisters.
Critical events source indication register
(Block_base 0x0C00 + Register_offset 0x1E)
The bits in the Critical events source indication register are read only. Bit
SPI34_OVR reflects the logical OR result of all bits in the SPI-3 to SPI-4 critical
LIDassociatedinterruptindicationregisters.BitSPI43_OVRreflectsthelogical
ORresultofallbitsintheSPI-4toSPI-3criticalLIDinterruptindicationregisters.
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