88
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
6370 drw10
Valid Address
tRecovery
tWC
tWRW
tAH
tAV
tDHW
tDV
Write DBUS[7:0]
ADD[5:0]
WRB + CSB
Write cycle specification Intel non-multiplexed bus (MPM=1)
Symbol
Parameter
MIN
MAX
Unit
T
Internal main clock period (MCLK)
80
100
MHz
tWC
Writecycletime
2.5T+19
ns
tWRW
Valid WRB width
2.5T+14
ns
tAV
Delay from WRB to Valid Address
T/2-2
ns
tAH
Address to WRB hold time
2.5T+12
ns
tDV
Delay from WRB to valid write data
T/2-2
ns
tDHW
Write data to WRB hold time
2.5T+12
ns
tRecovery Recovery time from read cycle
5
ns
NOTE
:
1. RDB should be tied to a logic one.
Figure 40. Microprocessor parallel port Intel mode write timing diagram
TABLE 141 – MICROPROCESSOR PARALLEL PORT INTEL MODE WRITE TIMING