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| 型號： | IDT88P8342BHI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 55/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標準包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8342BHI |
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59
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
TABLE 56 - SPI-4 INGRESS TO SPI-3 EGRESS FLOW
CONTROLREGISTER(REGISTER_OFFSET=0x01)
Field
Bits
Length
Initial Value
CREDIT_EN
0
1
0b0
BURST_EN
1
0b0
LOOP_BACK
2
1
0b0
Reserved
31:3
29
0x00
TABLE 57 - SPI-3 EGRESS TEST REGISTER
(REGISTER_OFFSET=0x02)
Field
Bits
Length
Initial Value
ADD_PAR_ERR
0
1
0b0
DAT_PAR_ERR
1
0b0
Reserved
7:2
6
0x00
PORT_ADDRESS
15:8
8
0x0F
LP
The LP programmed is associated to the LID with the same number
as the register address.
ENABLE
This bit is used to enable or disable the connection of a LID to
an LP.
0=LP disabled
1=LP enabled
BIT_REVERSAL This bit is used to reverse the bit ordering of each byte
of the SPI-3 interface on a per-LP basis.
0=Disable bit reversal for an LP
1=Enable bit reversal for an LP
9.3.4 Block base 0x0700 registers
SPI-3 egress configuration register (Block_base
0x0700 + Register_offset 0x00)
There is one SPI-3 egress configuration register per SPI-3 interface. The
SPI-3 egress configuration registers have read and write access. A SPI-3
egress configuration registers is used to control the poll sequence length of a
SPI-3 egress interface when the SPI-3 interface is in Link mode. The SPI-3
egress configuration register is used to add two cycles to STX or EOP as
required to interface to the attached device.
POLL_LENGTH Link layer poll sequence length when in Link mode. The
pollsequenceisfromtheLPassociatedwithLID0totheLPassociatedwiththe
LID for POLL_LENGTH - 1.
STX_SPACING This bit is used to enable or disable the adding of two
dummySTXcyclestoaSPI-3egressinterfacetomeettheneedsofanattached
device.
0= No dummy STX cycles are added to a SPI-3 egress.
1= Two dummy STX cycles are added to a SPI-3 egress
EOP_SPACING This bit is used to enable or disable the adding of two
dummyEOPcyclestoaSPI-3egressinterfacetomeettheneedsofanattached
device.
0= No dummy EOP cycles are added to a SPI-3 egress.
1= Two dummy EOP cycles are added to a SPI-3 egress
SPI-4 ingress to SPI-3 egress flow control register
(Block_base 0x0700 + Register_offset 0x01)
The SPI-4 ingress to SPI-3 egress flow control register has read and write
access. The bit fields of the SPI-4 ingress to SPI-3 egress flow control register
are described.
CREDIT_EN
CREDIT_EN Theflowcontrolinformationreceivedfrom
theattachedSPI-3deviceisintrepretedasstatusorcreditinformationasselected
bytheCREDIT_ENbitintheSPI-4ingresstoSPI-3egressflowcontrolRegister.
If the status mode is used, data will be egressed until the status is changed by
the attached SPI-3 device. If the credit mode is used, the SPI-3 egress will
transmitonlyonepacketfragmentandthenwaitforanupdateintheinternalbuffer
segment pool status before sending another packet fragment.
0=Statusmode
1=Credit mode
BURST_EN
MultipleBurstEnableallowsmorethanonebursttobesent
to an LP. When this feature is not enabled, only one burst per LP is allowed into
the SPI-3 egress buffers.
0=Disable burst enable
1=Enable burst enable
LOOP_BACK
In this mode the contents of a SPI-3 ingress are directly
transferred to a SPI-3 egress buffers of the same port. This mode is useful for
off-linediagnostics.
0=Disable loopback
1=Enable loopback
SPI-3 egress test register (Block_base 0x0700 +
Register_offset 0x02)
TABLE 55 - SPI-3 EGRESS CONFIGURATION
REGISTER(REGISTER_OFFSET=0x00)
Field
Bits
Length
Initial Value
POLL_LENGTH
5:0
6
0x0F
Reserved
7:6
2
0b00
STX_SPACING
8
1
0b0
EOP_SPACING
9
1
0b0
Reserved
31:10
22
0x00
The SPI-3 egress test register has read and write access. A single address
parity error is introduced on a SPI-3 egress LP through the ADD_PAR_ERR
bit field. A single data parity error is introduced on a SPI-3 egress LP through
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