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| 型號： | IDT88P8342BHI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 61/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標準包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8342BHI |
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64
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
9.3.7 Block base 0x0100 registers
SPI-3 ingress packet length configuration register
(Block_base 0x1000 + Register_offset 0x00-0x3F)
TABLE 72 - SPI-3 INGRESS PACKET LENGTH
CONFIGURATIONREGISTER
Field
Bits
Length
Initial Value
MIN_LENGTH
7:0
8
0x40
Reserved
15:8
8
0x00
MAX_LENGTH
29:16
14
0x5EE
There is one set of SPI-3 ingress packet length configuration registers per
SPI-3 ingress interface. Each SPI-3 ingress interface has 64 registers, one for
eachoftheallowedLIDssupportedperSPI-3interface.Eachregisterhasread
and write access. The minimum and maximum packet lengths per LID are
provisioned using the SPI-3 ingress packet length configuration register. The
bit fields of a SPI-3 ingress packet length configuration register are described.
MIN_LENGTH
SPI-3 ingress minimum packet length. The minimum
packetlengthisprogrammedfrom0to255bytes.Theresolutionoftheminimum
packet length is one byte.
MAX_LENGTH SPI-3 ingress maximum packet length. The maximum
packet length is programmed from 0 to 16,383 bytes. The resolution of the
maximum packet length is one byte.
9.3.8 Block base 0x1100 registers
SPI-4 egress port descriptor table (Block_base
0x1100 + Register_offset 0x00-0x3F)
TABLE 73 - SPI-4 EGRESS PORT DESCRIPTOR
TABLE (64 ENTRIES)
Field
Bits
Length
Initial Value
MAX_BURST_H
3:0
4
0xF
MAX_BURST_S
7:4
4
0xF
DIRECTION
9:8
2
0x3
Reserved
31:10
22
0x000
There are two sets of SPI-4 egress port descriptor tables, one per SPI-3
interface. The minimum and maximum SPI-4 egress burst lengths per LID are
provisioned using aSPI-4 egress port descriptor table. Each SPI-4 egress port
descriptor table has read and write access. The bit fields of the SPI-4 egress
port descriptor table are described. These fields need to be programmed only
for SPI-4 egress (DIRECTION=0 in Table 74-SPI-4 egress direction code
assignment.
MAX_BURST_H
SPI-4 egress per-LID burst length when the attached
device has declared hungry through the FIFO status channel. The number in
the MAX_BURST_H field is taken to mean that one more than that number
multipliedby16isthemaximumhungryburstlength.Forexample,programming
thenumber3intotheMAX_BURST_Hfieldresultsinamaximumhungryburst
size of (3 + 1) 9.3.9 Block base 0x1200 registers
MAX_BURST_S
SPI-4 egress per-LID burst length when the attached
device has declared starving through the FIFO status channel. The number in
the MAX_BURST_S field is taken to mean that one more than that number
multiplied by 16 is the maximum starving burst length. For example, program-
mingthenumber7intotheMAX_BURST_Sfieldresultsinamaximumstarving
burst size of (7 + 1) x 16 = 128 bytes. The MAX_BURST_S field should not be
set to less than the MAX_BURST_H field.
DIRECTION
TheSPI-4egresstrafficcanbecapturedbythemicropro-
cessor, directed to a SPI-3 egress port, to the SPI-4 egress port, or discarded.
The Path selection is defined for each of the 64 LIDs by the associated
DIRECTION field as shown in the following table.
DIRECTION
Path
00
SPI-4
01
AssociatedSPI-3
10
Capture to microprocessor
11
Discard
TABLE 74 - SPI-4 EGRESS DIRECTION CODE
ASSIGNMENT
TABLE 75 - SPI-3 INGRESS PORT DESCRIPTOR
TABLE (BLOCK_BASE 0x1200)
Field
Bits
Length
Initial Value
M
8:0
9
0x000
Reserved
15:9
7
0x00
Reserved
20:16
5
0x00
Reserved
23:21
3
0x0
FREE_SEGMENT
28:24
5
0x00
Reserved
31:29
3
0x0
9.3.9 Block base 0x1200 registers
SPI-3 ingress port descriptor tables (Block_base
0x1200 + Register_offset 0x00-0x3F)
There is one set of 64 SPI-3 ingress port descriptor tables per SPI-3 ingress
interface. The SPI-3 ingress port descriptor tables are at Block_base 0x1200
and have read and write access. Each SPI-3 ingress interface has 64 table
entries for per-LID provisioning of M and FREE_SEGMENT fields. The SPI-
3 ingress port descriptor tables are used to control the amount of buffering and
the free segment backpressure threshold of the available buffer segment pool
for a SPI-3 ingress on a per-LID basis.
Each SPI-3 buffer segment pool is 128 Kbytes, divided into 508 segments
of 256 bytes per segment. These 508 segments are shared among the LIDs
initiallyprogrammedintotheNR_LIDfields.ASPI-3ingressLIDcanbeallocated
themaximumnumberofsegmentsoutoftheavailablebuffersegments,orcan
be programmed to fewer segments by decreasing the M field.
The FREE_SEGMENT field is used, along with the M field, to set the free
segment backpressure threshold for a LID on a SPI-3 ingress.
M
Thenumberof256-bytebufferpoolsegmentsonaSPI-3ingressport
allocated to a LID. The range of M is 0x000 to 0x1FC (508 base 10), but can
not exceed the number set by the choice of NR_LID [Block_base 0x1300 +
Register_offset0x00].
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IDT88P8344 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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