參數(shù)資料
型號: IDT82P5088BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 33/81頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝: 90
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 8
電源電壓: 1.8V, 3.3V
功率(瓦特): 2.57W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 托盤
包括: 集成式時鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
39
February 5, 2009
3.11 GENERAL PURPOSE I/O
The IDT82P5088 provides two general purpose digital I/O pins: GPIO1,
GPIO0. These two pins can be considered as digital Input or Output port
by the DIR1 bit (GPIO, 06H) and DIR0 bit (GPIO, 06H) respectively. If the
GPIO1 and GPIO0 are configured as Input port, the LEVEL1 bit (GPIO,
06H) and the LEVEL0 bit (GPIO, 06H) are used to reflect the level of the
GPIO1 pin and the GPIO0 pin respectively. If the GPIO1 and GPIO0 are
configured as Output port, the content in the LEVEL1 bit and LEVEL0 bit
determines the logic value of GPIO1 pin and GPIO0 pin respectively.
3.12 RESET OPERATION
The chip can be reset in two ways:
Software Reset: Writing to the RST register (04H) will reset the chip
in 1 us.
Hardware Reset: Asserting the RESET pin low for a minimum of 100
ns will reset the chip.
DuringHardwareReset,thedevicerequiresanactiveclockonMCLK.
For T1/J1 operation, bit TE_MODE(T1E1 mode, 20H...) is set after
reset.Beforeaccessinganyotherregistersadelayof50usisrequired
to allow the internal clocking to be settled.
After reset, all drivers output are in high impedance state, all the internal
flip-flops are reset, and all the registers are initialized to default values.
When performing a software reset, the TE_MODE bit (T1E1 mode, 20H...)
will not be reset and stay with the set value.
3.13 POWER SUPPLY
This chip uses 3.3 V and 1.8 V power supply.
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