參數(shù)資料
型號(hào)： IDT82P5088BBG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 15/81頁
文件大小： 0K
描述： IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝： 90
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 8
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.57W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 托盤
包括： 集成式時(shí)鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
22
February 5, 2009
3.2.4
TRANSMIT PATH LINE INTERFACE
The transmit line interface consists of TTIPn pin and TRINGn pin. The
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 32H...) can be set to choose 75
, 100 ,
110
or 120 internal impedance of TTIPn/TRINGn. If T_TERM[2] is set
to ‘1’, the internal impedance matching circuit will be disabled. In this case,
the external impedance matching circuit will be used to realize the imped-
ance matching. For T1/J1 mode, the external impedance matching circuit
forthetransmitterisnotsupported.Figure-9showstheappropriateexternal
components to connect with the cable for one channel. Table-14 is the list
of the recommended impedance matching for transmitter.
The TTIPn/TRINGn can be turned into high impedance globally by pull-
ing THZ pin to high or individually by setting the T_HZ bit (TCF1, 23H...) to
‘1’. In this state, the internal transmit circuits are still active.
Besides, in the following cases, TTIPn/TRINGn will also become high
impedance:
Loss of MCLK: all TTIPn/TRINGn pins become high impedance;
Loss of TCLKn: corresponding TTIPn/TRINGn become HZ (excep-
tions: Remote Loopback; Transmit internal pattern by MCLK);
Transmit path power down;
After software reset; pin reset and power on.
Note: The precision of the resistors should be better than ± 1%
3.2.5
TRANSMIT PATH POWER DOWN
The transmit path can be powered down individually by setting the
T_OFF bit (TCF0, 22H...) to ‘1’. In this case, the TTIPn/TRINGn pins are
turned into high impedance.
3.2.6
TRANSMIT JITTER ATTENUATOR
The Transmit Jitter Attenuator of each link can be chosen to be used
or not. This selection is made by the TJA_E bit (TJACF, 21H...).
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
Figure-7 Jitter Attenuator
The FIFO is used as a pool to buffer the jittered input data, then the
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the TJA_DP[1:0]
bits (TJACF, 21H...). Accordingly, the constant delay produced by the
Jitter Attenuator is 16 bits, 32 bits or 64 bits. The 128-bit FIFO is used
when large jitter tolerance is expected, and the 32-bit FIFO is used in
delay sensitive applications.
The DPLL is used to generate a de-jittered clock to clock out the data
stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter which
frequency is lower than the CF passes through the DPLL without any
attenuation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or
1.26 Hz, as selected by the TJA_BW bit (TJACF, 21H...). In E1 applica-
tions, the CF of the DPLL can be 6.77 Hz or 0.87 Hz, as selected by the
TJA_BW bit (TJACF, 21H...). The lower the CF is, the longer time is
needed to achieve synchronization.
If the incoming data moves faster than the outgoing data, the FIFO
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
Table-14 Impedance Matching for Transmitter
Cable Configuration
Internal Termination
External Termination
T_TERM[2:0]
PULS[3:0]
RT
T_TERM[2:0]
PULS[3:0]
RT
E1/75
000
0000
0
1XX
0001
9.4
E1/120
001
0001
T1/0~133 ft
010
0010
-
T1/133~266 ft
0011
T1/266~399 ft
0100
T1/399~533 ft
0101
T1/533~655 ft
0110
J1/0~655 ft
011
0111
0 dB LBO
010
1000
-7.5 dB LBO
1001
-15.0 dB LBO
1010
-22.5 dB LBO
1011
FIFO
32/64/128
DPLL
Jittered Data
De-jittered Data
Jittered Clock
De-jittered Clock
write
pointer
read
pointer
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