參數(shù)資料
型號: IDT82P5088BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/81頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝: 90
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 8
電源電壓: 1.8V, 3.3V
功率(瓦特): 2.57W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 托盤
包括: 集成式時鐘適配器
2009 Integrated Device Technology, Inc.
DSC-7216/-
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
February 5, 2009
Universal Octal T1/E1/J1 LIU with Inte-
grated Clock Adapter
IDT82P5088
FEATURES
Eight channel T1/E1/J1 long haul/short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024
KHz
Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
3.3 V and 1.8 V power supply with 5 V tolerant inputs
Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703,G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR 12/13
- AT&T Pub 62411
Per channel software selectable on:
- Wave-shapingtemplatesforshorthaulandlonghaulLBO(LineBuild
Out)
- Line terminating impedance (T1:100
, J1:110 , E1:75 /120 )
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path and transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 215-1 PRBS polynomials for E1
- QRSS (Quasi Random SequenceSignals)generationand detection
with 220-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Per channel cable attenuation indication
Adaptive receive sensitivity
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection for line drivers
LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces
Package:
Available in 256-pin PBGA
Green package options available
DESCRIPTION
The IDT82P5088 is an eight port line intereface that can be configured
perporttoanycombinationofT1,E1orJ1ports.Inreceivepath,anAdaptive
Equalizer is integrated to remove the distortion introduced by the cable
attenuation. The IDT82P5088 also performs clock/data recovery, AMI/
B8ZS/HDB3 line decoding and detects and reports the LOS conditions. In
transmit path, there is an AMI/B8ZS/HDB3 encoder, Waveform Shaper,
LBOs and Jitter Attenuator for each channel. The Jitter Attenuators in trans-
mit path and receive path both can be disabled. The IDT82P5088 supports
both Single Rail and Dual Rail system interfaces. To facilitate the network
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
each channel, and different types of loopbacks can be set on a per channel
basis. Four different kinds of line terminating impedance, 75
, 100 , 110
and 120 are selectable on a per channel basis. The chip also provides
driver short-circuit protection and supports JTAG boundary scanning.
The IDT82P5088 can be used in SDH/SONET, LAN, WAN, Routers,
Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay
Access Devices, CSU/DSU equipment, etc.
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