參數(shù)資料
型號: IDT82P5088BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 22/81頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 OCTAL 256PBGA
標準包裝: 90
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 8
電源電壓: 1.8V, 3.3V
功率(瓦特): 2.57W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 托盤
包括: 集成式時鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
29
February 5, 2009
3.3.12.2AIS DETECTION
The Alarm Indication Signal can be detected by the IDT82P5088 when
the Clock&Data Recovery unit is enabled. The status of AIS detection is
reflected in the AIS_S bit (STAT0, 36H...). In T1/J1 applications, the criteria
for declaring/clearing AIS detection are in compliance with the ANSI
T1.231. In E1 applications, the criteria for declaring/clearing AIS detection
comply with the ITU G.775 or the ETSI 300233, as selected by the LAC bit
(MAINT1,2CH...). Table-21 summarizes different criteria for AIS detection
Declaring/Clearing.
Table-20 LOS Declare and Clear Criteria for Long Haul Mode
Control bit
LOS declare threshold
LOS clear threshold
Note
TEMODE
LAC
LOS[4:0]
Q (dB)
1=T1/J1
0
T1.231
00000
00001
10001
10101
10110-11111
-4
-6
-38
-46
-48
Level < Q
N=175 bits
Level > Q+ 4dB
M=128 bits
12.5% mark density
<100 consecutive zeroes
1
-
00000
00110
-4
-16
Level < Q
N=1544 bits
Level > Q+ 4dB
M=128 bits
12.5% mark density
<100 consecutive zeroes
I.431 Level detect range is -18 to -30 dB.
I.431 00111
01101
-18
-30
-
01110
10001
10101
10110-11111
-32
-38
-46
-48
0=E1
0
-
00000
00010
-4
-8
Level < Q
N=32 bits
Level > Q+ 4dB
M=32 bits
12.5% mark density
<16 consecutive zeroes
G.775 Level detect range is -9 to -35 dB.
G.775
00011
10000
-10
-36
-
10001
10101(default)
10110-11111
-38
-46
-48
1
-
00000
-4
Level < Q
N=2048 bits
Level > Q+ 4dB
M=32 bits
12.5% mark density
<16 consecutive zeroes
I.431 Level detect range is -6 to -20 dB.
I.431/
ETSI
00001
01000
-6
-20
-
01001
10101(default)
10110-11111
-22
-46
-48
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