參數(shù)資料
型號: IDT82P5088BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 32/81頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝: 90
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 8
電源電壓: 1.8V, 3.3V
功率(瓦特): 2.57W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 托盤
包括: 集成式時鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
38
February 5, 2009
3.10 INTERRUPT HANDLING
AnactivelevelontheINTpinrepresentsaninterruptoftheIDT82P5088.
The INT_CH[7:0] bits (INTCH, 09H) should be read to identify which chan-
nel(s) generate the interrupt.
The interrupt event is captured by the corresponding bit in the Interrupt
Status Register (INTS0, 3AH...) or (INTS1, 3BH...). Every kind of interrupt
canbeenabled/disabledindividuallybythecorresponding bitinthe register
(INTENC0, 33H...) or (INTENC1, 34H...). Some event is reflected by the
corresponding bit in the Status Register (STAT0, 36H...) or (STAT1,
37H...), and the Interrupt Trigger Edge Selection Register can be used to
determine how the Status Register sets the Interrupt Status Register.
After the Interrupt Status Register (INTS0, 3AH...) or (INTS1, 3BH...) is
read, the corresponding bit indicating which channel generates the inter-
rupt in the INTCH register (09H) will be reset. Only when all the pending
interrupt is acknowledged through reading the Interrupt Status Registers
of all the channels (INTS0, 3AH...) or (INTS1, 3BH...) will all the bits in the
INTCH register (09H) be reset and the INT pin become inactive.
There are totally fourteen kinds of events that could be the interrupt
source for one channel:
(1).LOS Detected
(2).AIS Detected
(3).Driver Failure Detected
(4).TCLK Loss
(5).Synchronization Status of PRBS
(6).PRBS Error Detected
(7).Code Violation Received
(8).Excessive Zeros Received
(9).JA FIFO Overflow/Underflow
(10).Inband Loopback Code Status
(11).Equalizer Out of Range
(12).One-Second Timer Expired
(13).Error Counter Overflow
(14).Arbitrary Waveform Generator Overflow
Table-26 is a summary of all kinds of interrupt and their associated Sta-
tus bit, Interrupt Status bit, Interrupt TriggerEdge Selectionbit andInterrupt
Mask bit.
Table-26 Interrupt Event
Interrupt Event
Status bit
(STAT0, STAT1)
Interrupt Status bit
(INTS0, INTS1)
Interrupt Edge Selection bit
(INTES)
Interrupt Mask bit
(INTENC0, INTENC1)
LOS Detected
LOS_S
LOS_IS
LOS_IES
LOS_IE
AIS Detected
AIS_S
AIS_IS
AIS_IES
AIS_IE
Driver Failure Detected
DF_S
DF_IS
DF_IES
DF_IE
TCLKn Loss
TCLK_LOS
TCLK_LOS_IS
TCLK_IES
TCLK_IE
Synchronization Status of PRBS/QRSS
PRBS_S
PRBS_IS
PRBS_IES
PRBS_IE
PRBS/QRSS Error
ERR_IS
ERR_IE
Code Violation Received
CV_IS
CV_IE
Excessive Zeros Received
EXZ_IS
EXZ_IE
JA FIFO Overflow
JAOV_IS
JAOV_IE
JA FIFO Underflow
JAUD_IS
JAUD_IE
Equalizer Out of Range
EQ_S
EQ_IS
EQ_IES
EQ_IE
Inband Loopback Activate Code Status
NLPA_S
NLPA_IS
NLPA_IES
NLPA_IE
Inband Loopback Deactivate Code Status
NLPD_S
NLPD_IS
NLPD_IES
NLPD_IE
One-Second Timer Expired
TMOV_IS
TIMER_IE
Error Counter Overflow
CNT_OV_IS
CNT_IE
Arbitrary Waveform Generator Overflow
DAC_OV_IS
DAC_OV_IE
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