參數(shù)資料
型號: IDT821034
廠商: Integrated Device Technology, Inc.
元件分類: Codec
英文描述: QUAD PCM CODEC WITH PROGRAMMABLE GAIN
中文描述: 四的PCM編解碼器,具有可編程增益
文件頁數(shù): 7/52頁
文件大小: 609K
代理商: IDT821034
7
INDUSTRIAL TEMPERATURE RANGES
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
Pin No.
Name
Type
QFP144 BGA160
Description
Hardware/Host Control Mode
MODE2: Control Mode Select 2
The signal on this pin determines which control mode is selected to control the device:
MODE2
Control Interface
Low
Control by Hardware mode
VDDIO/2
Control by Serial Host Interface
High
Control by Parallel Host Interface
Hardware control pins include MODE[2:0], TS[2:0], LOOP[7:0], CODE, CLKE, JAS and OE.
Serial host Interface pins include
CS
, SCLK, SDI, SDO and
INT
.
Parallel host Interface pins include
CS
, A[4:0], D[7:0],
WR
/
DS
,
RD
/R/
W
, ALE/
AS
,
INT
and RDY/
ACK
. The
device supports multiple parallel host interface as follows (
refer to MODE1 and MODE0 pin descriptions
below for details
):
MODE[2:0]
Host Interface
100
Non-multiplexed Motorola mode interface.
101
Non-multiplexed Intel mode interface.
110
Multiplexed Motorola mode interface.
111
Multiplexed Intel mode interface.
MODE1: Control Mode Select 1
In parallel host mode, the parallel interface operates with separate address bus and data bus when this
pin is Low, and operates with multiplexed address and data bus when this pin is High.
In serial host mode and hardware mode, this pin should be grounded.
MODE0: Control Mode Select 0
In host mode, the parallel host interface is configured for Motorola compatible hosts when this pin is Low,
or for Intel compatible hosts when this pin is High.
CODE: Line Code Rule Select
In hardware control mode, the HDB3 encoder/decoder is enabled when this pin is Low, and AMI
encoder/decoder is enabled when this pin is High. The selections affect all the channels.
In serial host mode, this pin should be grounded.
CS
: Chip Select (Active Low)
In host mode, this pin is asserted low by the host to enable host interface. A transition from High to Low
must occur on this pin for each Read/Write operation and the level must not return to High until the
operation is over.
JAS: Jitter Attenuator Select
In hardware control mode, this pin globally determines the Jitter Attenuator position:
JAS
Jitter Attenuator (JA) Configuration
Low
VDDIO/2
High
MODE2
I
(Pulled
to
VDDIO
/2)
11
E2
MODE1
I
43
K2
MODE0
/CODE
I
88
H12
JA in transmit path
JA not used
JA in receive path
CS
/JAS
I
(Pulled
to
VDDIO
/2)
87
J11
PIN DESCRIPTION (CONTINUED)
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