參數(shù)資料
型號(hào)： IDT821034
廠商： Integrated Device Technology, Inc.
元件分類： Codec
英文描述： QUAD PCM CODEC WITH PROGRAMMABLE GAIN
中文描述： 四的PCM編解碼器，具有可編程增益
文件頁(yè)數(shù)： 36/52頁(yè)
文件大?。?/td> 609K
代理商： IDT821034
36
INDUSTRIAL TEMPERATURE RANGES
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
STATE
DESCRIPTION
Test Logic
Reset
In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device
initializes the instruction register with the IDCODE instruction.
Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input
is held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. The device
processor automatically enters this state at power-up.
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as
TMS is held low. The instruction register and all test data registers retain their previous state. When TMS is high and a
rising edge is applied to TCK, the controller moves to the Select-DR state.
This is a temporary controller state and the instruction does not change in this state. The test data register selected
by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this
state, the controller moves into the Capture-DR state and a scan sequence for the selected test data register is initiated.
If TMS is held high and a rising edge applied to TCK, the controller moves to the Select-IR-Scan state.
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or
SAMPLE/PRELOAD. The instruction does not change in this state. The other test data registers, which do not have
parallel input, are not changed. When the TAP controller is in this state and a rising edge is applied to TCK, the
controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
In this controller state, the test data register connected between TDI and TDO as a result of the current instruction
shifts data on stage toward its serial output on each rising edge of TCK. The instruction does not change in this state.
When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if
TMS is high or remains in the Shift-DR state if TMS is low.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller
to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to
TCK, the controller enters the Pause-DR state. The test data register selected by the current instruction retains its
previous value and the instruction does not change during this state.
The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the
serial path between TDI and TDO. For example, this state could be used to allow the tester to reload its pin memory
from disk during application of a long test sequence. The test data register selected by the current instruction retains its
previous value and the instruction does not change during this state. The controller remains in this state as long as TMS
is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller
to enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to
TCK, the controller enters the Shift-DR state. The test data register selected by the current instruction retains its
previous value and the instruction does not change during this state.
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in
response to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the
Boundary Scan Register is selected, data is latched into the parallel output of this register from the shift-register path on
the falling edge of TCK. The data held at the latched parallel output changes only in this state. All shift-register stages in
the test data register selected by the current instruction retain their previous value and the instruction does not change
during this state.
This is a temporary controller state. The test data register selected by the current instruction retains its previous
state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR
state, and a scan sequence for the instruction register is initiated. If TMS is held high and a rising edge is applied to
TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change during this state.
In this controller state, the shift register contained in the instruction register loads a fixed value of ‘100’ on the rising
edge of TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current
instruction retain their value and the instruction does not change during this state. When the controller is in this state
and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or the Shift-IR state if
TMS is held low.
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data
one stage towards its serial output on each rising edge of TCK. The test data register selected by the current instruction
retains its previous value and the instruction does not change during this state. When the controller is in this state and a
rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or remains in the Shift-IR state
if TMS is held low.
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Capture-IR
Shift-IR
TABLE - 18. TAP CONTROLLER STATE DESCRIPTION
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參數(shù)描述
IDT821034DN 功能描述:IC PCM CODEC QUAD MPI 52-PQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821034DNG 功能描述:IC PCM CODEC QUAD MPI 52-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821054 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
IDT821054A 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
IDT821054APF 功能描述:IC PCM CODEC QUAD MPI 64-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
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