參數(shù)資料
型號(hào)： IDT821034
廠商： Integrated Device Technology, Inc.
元件分類： Codec
英文描述： QUAD PCM CODEC WITH PROGRAMMABLE GAIN
中文描述： 四的PCM編解碼器，具有可編程增益
文件頁數(shù)： 18/52頁
文件大?。?/td> 609K
代理商： IDT821034
18
INDUSTRIAL TEMPERATURE RANGES
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
LOOPBACK MODE
The device provides four different diagnostic loopback configura-
tions: Digital Loopback, Analog Loopback, Remote Loopback and
Dual Loopback. In host mode, these functions are implemented by
programming the registers
DLB
,
ALB
or
RLB
. In hardware mode,
only analog loopback and remote loopback can be selected by pull-
ing pin LPn to High and Low respectively.
Digital Loopback
By programming the bits of register
DLB
, each channel of the de-
vice can be set in Local Digital Loopback. In this configuration, the
data and clock to be transmitted, after passing the encoder, is looped
back to jitter attenuator (if enabled) and decoder in the receive path,
then output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be
transmitted are still output on TTIPn and TRINGn while the data re-
ceived on RTIPn and RRINGn are ignored. The Loss Detector is still
in use.
Figure-11
shows the process.
Analog Loopback
By programming the bits of
ALB
register or pulling pin LPn to
High, each channel of the device can be set in Analog Loopback. In
this configuration, the data to be transmitted output from the line driver
are internally looped back to the slicer and peak detector in the
receive path and output on RCLKn, RDn/RDPn and CVn/RDNn. The
data to be transmitted are still output on TTIPn and TRINGn while the
data received on RTIPn and RRINGn are ignored. The Loss Detector
is still in use.
Figure-12
shows the process.
The TTIPn and RTIPn, TRINGn and RRINGn cannot be connected
directly to do the external analog loopback test. Line impedance
loading is required to conduct the external analog loopback test.
Remote Loopback
By programming the bits of
RLB
register or pulling pin LPn to Low,
each channel of the device can be set in Remote Loopback. In this
configuration, the data and clock recovered by the Clock and Data
Recovery circuits are looped to waveform shaper and output on
TTIPn and TRINGn. The jitter attenuator is also included in loopback
when enabled in the transmit or receive path. The received data and
clock are still output on RCLKn, RDn/RDPn and CVn/RDNn while the
data to be transmitted on TCLKn, TDn/TDPn and BPVIn/TDNn are
ignored. The Loss Detector is still in use.
Figure-13
shows the
process.
Dual Loopback
Dual Loopback mode is set by setting both bit DLBn in register
DLB
and bit RLBn in register
RLB
to ‘1’. In this configuration, after
passing the encoder, the data and clock to be transmitted are looped
back to decoder directly and output on RCLKn, RDn/RDPn and CVn/
RDNn. The recovered data from RTIPn and RRINGn are looped back
to waveform shaper through JA (if selected) and output on TTIPn and
TRINGn. The Loss Detector is still in use.
Figure-14
shows the proc-
ess.
Transmit All Ones
In hardware mode, the TAOS mode is set by pulling TCLKn High
for more than 16 MCLK cycles. In host mode, TAOS mode is set by
programming register
TAO
. In addition, automatic TAO signals are in-
serted by setting register
ATAO
when Loss of Signal occurs. Note that
the TAOS generator adopts MCLK as a timing reference. In order to
assure that the output frequency is within specification limits, MCLK
must have the applicable stability.
This TAOS mode and Digital Loopback or Analog Loopback can
be configured simultaneously.
Figure-15
shows their process.
Figure - 12. Analog Loopback
Jitter
Attenuator
Jitter
Attenuator
HDB3/AMI
Decoder
HDB3/AMI
Encoder
Analog
Loopback
Slicer
Peak
Detector
CLK&Data
Recovery
(DPLL)
Line
Driver
Waveform
Shaper
LOS
Detector
One of Eight Identical Channels
RTIPn
RRINGn
TTIPn
TRINGn
LOSn
RCLKn
RDn/RDPn
CVn/RDNn
TCLKn
TDn/TDPn
BPVIn/TDNn
Transmit
All Ones
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