參數(shù)資料
型號： IDT821034
廠商： Integrated Device Technology, Inc.
元件分類： Codec
英文描述： QUAD PCM CODEC WITH PROGRAMMABLE GAIN
中文描述： 四的PCM編解碼器，具有可編程增益
文件頁數(shù)： 32/52頁
文件大?。?/td> 609K
代理商： IDT821034
32
INDUSTRIAL TEMPERATURE RANGES
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
IEEE STD 1149.1 JTAG TEST ACCESS
PORT
The IDT82V2048 supports the digital Boundary Scan Specification
as described in the IEEE 1149.1 standards.
The boundary scan architecture consists of data and instruction
registers plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the Test Mode Select (TMS) and
Test Clock (TCK) input pins. Data is shifted into the registers via the
Test Data Input (TDI) pin, and shifted out of the registers via the Test
Data Output (TDO) pin. Both TDI and TDO are clocked at a rate deter-
mined by TCK.
The JTAG boundary scan registers includes BSR (Boundary
Scan Register), IDR (Device Identification Register), BR (Bypass
Register) and IR (Instruction Register). These will be described in the
following pages.
Refer to Figure-18
for architecture.
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR)
The
IR
(Instruction Register) with instruction decode block is used to
select the test to be executed or the data register to be accessed or both.
The instructions are shifted in LSB first to this 3-bit register.
See Table-
15 for details of the codes and the instructions related.
JTAG DATA REGISTER
Device Identification Register (IDR)
The IDR can be set to define the producer number, part number and
the device revision, which can be used to verify the proper version or
revision number that has been used in the system under test.
The IDR
is 32 bits long and is partitioned as in
Table-16.
Data from the IDR is
shifted out to TDO LSB first.
Figure - 18. JTAG Architecture
BSR
(Boundary Scan Register)
IDR
(Device Identification Register)
BR
(Bypass Register)
IR
(Instruction Register)
MUX
TDO
TDI
TCK
TMS
TRST
Control<6:0>
M
Select
Tristate Enable
TAP
(Test Access Port)
Controller
parallel latched output
Digital output pins
Digital input pins
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT821034DN 功能描述:IC PCM CODEC QUAD MPI 52-PQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821034DNG 功能描述:IC PCM CODEC QUAD MPI 52-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821054 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
IDT821054A 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
IDT821054APF 功能描述:IC PCM CODEC QUAD MPI 64-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
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