- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377487 > IDT821034 (Integrated Device Technology, Inc.) QUAD PCM CODEC WITH PROGRAMMABLE GAIN PDF資料下載
參數(shù)資料
| 型號： | IDT821034 |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | Codec |
| 英文描述： | QUAD PCM CODEC WITH PROGRAMMABLE GAIN |
| 中文描述： | 四的PCM編解碼器，具有可編程增益 |
| 文件頁數(shù)： | 13/52頁 |
| 文件大小： | 609K |
| 代理商： | IDT821034 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
13
INDUSTRIAL TEMPERATURE RANGES
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
RECEIVER
In receive path, the line signals couple into RRINGn and RTIPn via
a transformer and are converted into RZ digital pulses by a data
slicer. Adaptation for attenuation is achieved using an integral peak
detector that sets the slicing levels. Clock and data are recovered
from the received RZ digital pulses by a digital phase-locked loop that
provides excellent jitter accommodation. After passing through the
selectable jitter attenuator, the recovered data are decoded using
HDB3 or AMI line code rules and clocked out of pin RDn in single rail
mode, or presented on RDPn/RDNn in an undecoded dual rail NRZ
format. Loss of signal, alarm indication signal, line code violations and
excessive zero are detected. These various changes in status may
be enabled to generate interrupts.
Peak Detector and Slicer
The slicer determines the presence and polarity of the received
pulses. In data recovery mode, the raw positive slicer output appears
on RDPn while the negative slicer output appears on RDNn. In clock
and data recovery mode, the slicer output is sent to Clock and Data
Recovery circuit for abstracting retimed data and optional decoding.
The slicer circuit has a built-in peak detector from which the slicing
threshold is derived. The slicing threshold is default to 50% (typical) of
the peak value.
Signals with an attenuation of up to 12 dB (from 2.4V) can be re-
covered accurately by the receiver. To provide immunity from impul-
sive noise, the peak detectors are held above a minimum level of
0.150 V typically, despite the received signal level.
Clock and Data Recovery
The function of Clock and Data Recovery is accomplished by
Digital Phase Locked Loop (DPLL). The DPLL is clocked 16 times of
the received clock rate, i.e. 32.768 MHz in E1 mode. The recovered
data and clock from DPLL is then sent to the selectable Jitter
Attenuator or decoder circuit for further processing.
RD/RDP and CV/RDN
Clock recovery
Pin CLKE
Slicer output
SDO
Low
RCLK
Active High
Active Low
SCLK
Active High
High
RCLK
Active High
Active High
SCLK
Active High
TABLE - 2. ACTIVE CLOCK EDGE AND ACTIVE LEVEL
The clock recovery and data recovery mode can be selected on
per channel basis by setting the bit CRSn in
e-CRS
.
When bit CRSn is
defaulted to ‘0’, the corresponding channel operates in data and clock
recovery mode. The recovered clock is output on pin RCLKn and re-
timed NRZ data are output on pin RDPn/RDNn in dual rail mode or on
RDn in single rail mode. When CRSn is ‘1’, dual rail with data
recovery mode is enabled in the corresponding channel and the clock
recovery function is bypassed. In this condition, the analog line signal
are converted to RZ digital bit streams on the RDPn/RDNn pins and
internally connected to an EXOR which is fed to the RCLKn output for
external clock recovery applications.
Moreover, Pulling MCLK to H level, all the receivers will enter the
dual rail with data recovery mode. In this case,
e-CRS
is ignored.
HDB3/AMI Line Code Rule
Selectable HDB3 or AMI line coding/decoding is provided when the
device is configured in single rail mode. HDB3 rules is enabled by set-
ting bit CODE in register
GCF
(global control configuration) to ‘0’ or
pulling pin CODE to Low. AMI rule is enabled by setting bit CODE in
GCF
to ‘1’ or pulling pin CODE to High. All the setting above are ef-
fected to eight channels.
Individual line code rule selection for each channel, if need, is
available by setting bit SINGn in
e-SING
to ‘1’ (to activate bit CODEn in
e-CODE
) and programming bit CODEn to select line code rules in the
corresponding channel: ‘0’ for HDB3, while ‘1’ for AMI. In this case, the
value in bit CODE in
GCF
or pin CODE for global control is unaffected
in the corresponding channel and only affect in other channels.
In dual rail mode, the decoder/encoder are bypassed. Bit CODE in
GCF
, bit CODEn in
e-CODE
and pin CODE are ignored.
The configuration of the Line Code Rule is summarized in
Table-3.
TABLE - 1b. SYSTEM INTERFACE CONFIGURATION (Hardware Mode)
Hardware Mode
MCLK
clocked
clocked
H
L
TDNn
Interface
Single Rail mode 1
Dual Rail with Clock Recovery
H ( 16 MCLK)
pulse
pulse
pulse
Receive just slice the incoming data. Transmit is determined by the status of TCLKn.
Receive is power down. Transmit is determined by the status of TCLKn.
相關PDF資料 |
PDF描述 |
|---|---|
| IDT821054 | QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE |
| IDT821054PQF | QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE |
| IDT821064 | QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| IDT821064PQF | QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| IDT821068 | OCTAL PROGRAMMABLE PCM CODEC |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT821034DN | 功能描述:IC PCM CODEC QUAD MPI 52-PQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| IDT821034DNG | 功能描述:IC PCM CODEC QUAD MPI 52-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| IDT821054 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE |
| IDT821054A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE |
| IDT821054APF | 功能描述:IC PCM CODEC QUAD MPI 64-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復。