參數(shù)資料
型號(hào): IDT821034
廠商: Integrated Device Technology, Inc.
元件分類(lèi): Codec
英文描述: QUAD PCM CODEC WITH PROGRAMMABLE GAIN
中文描述: 四的PCM編解碼器,具有可編程增益
文件頁(yè)數(shù): 33/52頁(yè)
文件大?。?/td> 609K
代理商: IDT821034
33
INDUSTRIAL TEMPERATURE RANGES
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
TABLE - 15. INSTRUCTION REGISTER DESCRIPTION
IR CODE
INSTRUCTION
COMMENTS
000
Extest
The external test instruction allows testing of the interconnection to other devices. When the current
instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO.
The signal on the input pins can be sampled by loading the boundary scan register using the Capture-
DR state. The sampled values can then be viewed by shifting the boundary scan register using the
Shift-DR state. The signal on the output pins can be controlled by loading patterns shifted in through
input TDI into the boundary scan register using the Update-DR state.
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary
scan register is placed between TDI and TDO. The normal path between the IDT82V2058 logic and
the I/O pins is maintained. Primary device inputs and outputs can be sampled by loading the boundary
scan register using the Capture-DR state. The sampled values can then be viewed by shifting the
boundary scan register using the Shift-DR state.
The identification instruction is used to connect the identification register between TDI and TDO. The
device's identification code can then be shifted out using the Shift-DR state.
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The
instruction is used to bypass the device.
100
Sample / Preload
110
Idcode
111
Bypass
Bypass Register (BR)
The BR consists of a single bit. It can provide a serial path between
the TDI input and TDO output, bypassing the BSR to reduce test access
times.
Boundary Scan Register (BSR)
The BSR can apply and read test patterns in parallel to or from all
the digital I/O pins. The BSR is a 98 bits long shift register and is initialized
and read using the instruction EXTEST or SAMPLE/PRELOAD. Each
pin is related to one or more bits in the BSR.
Please refer to Table-17
for details of BSR bits and their functions.
TEST ACCESS PORT CONTROLLER
The TAP controller is a 16-state synchronous state machine.
Figure-
19
shows its state diagram. A description of each state follows. Note that
the figure contains two main branches to access either the data or
instruction registers. The value shown next to each state transition in
this figure states the value present at TMS at each rising edge of TCK.
Please refer to Table-18 for details of the state description.
BIT No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BIT SYMBOL
POUT0
PIN0
POUT1
PIN1
POUT2
PIN2
POUT3
PIN3
POUT4
PIN4
POUT5
PIN5
POUT6
PIN6
POUT7
PIN7
PIN SIGNAL
LP0
LP0
LP1
LP1
LP2
LP2
LP3
LP3
LP4
LP4
LP5
LP5
LP6
LP6
LP7
LP7
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
COMMENTS
TABLE - 17. BOUNDARY SCAN REGISTER DESCRIPTION
BIT No.
0
1~11
12~27
28~31
COMMENTS
Set to “1”
Producer Number
Part Number
Device Revision
TABLE - 16. DEVICE IDENTIFICATION REGISTER DESCRIPTION
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