參數(shù)資料
型號： IDT821034
廠商： Integrated Device Technology, Inc.
元件分類： Codec
英文描述： QUAD PCM CODEC WITH PROGRAMMABLE GAIN
中文描述： 四的PCM編解碼器，具有可編程增益
文件頁數(shù)： 6/52頁
文件大小： 609K
代理商： IDT821034
6
INDUSTRIAL TEMPERATURE RANGES
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
Pin No.
Name
Type
QFP144 BGA160
40
33
77
70
111
104
5
142
41
34
76
69
112
105
4
141
Description
RD0/RDP0
RD1/RDP1
RD2/RDP2
RD3/RDP3
RD4/RDP4
RD5/RDP5
RD6/RDP6
RD7/RDP7
CV0/RDN0
CV1/RDN1
CV2/RDN2
CV3/RDN3
CV4/RDN4
CV5/RDN5
CV6/RDN6
CV7/RDN7
O
Tri-state
P2
M2
M13
P13
A13
C13
C2
A2
P3
M3
M12
P12
A12
C12
C3
A3
RDn: Receive Data for Channel 0~7
In Single Rail mode, the received NRZ data is output on this pin. The data is decoded by AMI or HDB3
line code rule.
CVn: Code Violation for Channel 0~7
In Single Rail mode, the bipolar violation, code violation and excessive zeros will be reported by driving
pin CVn to high level for a full clock cycle. However, only bipolar violation is indicated when AMI
decoder is selected.
RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7
In Dual Rail mode with clock recovery, these pins output the NRZ data. A high signal on RDPn
indicates the receipt of a positive pulse on RTIPn/RRINGn while a high signal on RDNn indicates the
receipt of a negative pulse on RTIPn/RRINGn.
The output data at RDn or RDPn/RDNn are valid on the falling edges of RCLK when the CLKE input is
in High level, or valid on the rising edges of RCLK when CLKE is Low.
In Dual Rail mode without clock recovery, these pins output the raw RZ sliced data. In this data
recovery mode, the active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is Low,
RDPn/RDNn is active low. When pin CLKE is High, RDPn/RDNn is active high.
In hardware mode, RDn or RDPn/RDNn will remain active during LOS. In host mode, these pins will
either remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE
in register
GCF
(Global Configuration register)
.
RDn or RDPn/RDNn is set into high impedance when the corresponding receiver is power down.
RCLKn: Receive Clock for Channel 0~7
In clock recovery mode, this pin outputs the recovered clock from signal received on RTIPn/RRINGn.
The received data are clocked out of the device on rising edges of RCLKn if pin CLKE is low, or on
falling edges of RCLKn if pin CLKE is high.
In data recovery mode, RCLKn is the output of an internal exclusive OR (XOR) which is connected with
RDPn and RDNn. The clock is recovered from the signal on RCLKn externally.
If receiver n is power down, the corresponding RCLKn is in high impedance.
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
MCLK
O
Tri-state
39
32
78
71
110
103
6
143
10
P1
M1
M14
P14
A14
C14
C1
A1
E1
I
MCLK: Master Clock
This is the independent, free running reference clock. A clock of 2.048 MHz is supplied to this pin as
the clock reference of the device for normal operation.
In receive path, when MCLK is high, the device slices the incoming bipolar line signal into RZ pulse
(Data Recovery mode). When MCLK is low, all the receivers are power down, and the output pins
RCLKn, RDPn and RDNn are switched to high impedance.
In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn
pin description for detail).
Note that wait state generation via RDY/
ACK
is not available if MCLK is not provided.
LOSn: Loss of Signal Output for Channel 0~7
A high level on this pin indicates the loss of signal when there is no transition over a specified period of
time or hasn’t enough ones density in the received signal. The transition will return to low automatically
when there is enough transitions over a specified period of time with a certain ones density in the
received signal. The LOS assertion and desertion criteria are described in the
Functional Description
.
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
O
42
35
75
68
113
106
3
140
K4
K3
K12
K11
E11
E12
E3
E4
PIN DESCRIPTION (CONTINUED)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT821034DN 功能描述:IC PCM CODEC QUAD MPI 52-PQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821034DNG 功能描述:IC PCM CODEC QUAD MPI 52-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821054 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
IDT821054A 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
IDT821054APF 功能描述:IC PCM CODEC QUAD MPI 64-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
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