參數(shù)資料
型號(hào): IDT821034
廠商: Integrated Device Technology, Inc.
元件分類(lèi): Codec
英文描述: QUAD PCM CODEC WITH PROGRAMMABLE GAIN
中文描述: 四的PCM編解碼器,具有可編程增益
文件頁(yè)數(shù): 21/52頁(yè)
文件大?。?/td> 609K
代理商: IDT821034
21
INDUSTRIAL TEMPERATURE RANGES
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
Service the Interrupt
Read Interrupt Status Register
Read Corresponding Status
Register
Interrupt Allowed
Interrupt Condition
Exist
Yes
No
Figure - 17. Interrupt Service Routine
2. Status change in the
SC
(Short Circuit) Status Register(05H).
The automatic power driver circuit continuously monitors the output
drivers signal to update the specific bit in
SCM
which indicates pres-
ence or absence of the transmit line side short circuit condition.
3. Status change in the
AIS
(Alarm Indication Signal) Status
Register(13H). The AIS detector monitors the received signal to up-
date the specific bit in
AIS
which indicates presence or absence of a
AIS condition.
Interrupt Enable
The IDT82V2058 provides a latched interrupt output (
INT
) and the
three kinds of interrupts are all reported by this pin. When the Interrupt
Mask register (
LOSM
,
SCM
and
AISM
) is set to ‘1’, the Interrupt Sta-
tus register (
LOSI, SCI
and
AISI
) is enabled respectively. Whenever
there is a transition (‘0’ to ‘1’ or ‘1’ to ‘0’) in the corresponding Status
register, the Interrupt Status register will change into ‘1’, which means
an interrupt occurs, and there will be a transition from high to low on
INT
. An external pull-up resistor of approximately 10k
is required to
support the wire-OR operation of
INT
. When any of the three Interrupt
Mask registers is set to ‘0’ (the power-on default value is ‘0’), the cor-
responding Interrupt Status register is disabled and the transition on
status register is ignored.
Interrupt Clearing
When an interrupt occurs, the Interrupt Status registers
(
LOSI, SCI
and
AISI
) are read to identify the interrupt source. And these registers
will be cleared to ‘0’ after the corresponding Status register (
LOS, SC
and
AIS
) being read. The Status registers will be cleared once the
corresponding conditions are met.
Pin
INT
is pulled High when there are no pending interrupt left.
The interrupt handling in the interrupt service routine is showed
Fig-
ure-17.
A1
A3
A2
A4 A5 A6
D0 D1 D2 D3 D4 D5 D6 D7
R/
W
D0 D1 D2 D3 D4 D5 D6 D7
A7
Input Data Byte
Address/Command Byte
High Impedance
Driven while R/
W
=1
SDI
SDO
SCLK
CS
1
2
2
MODE[2:0]
100
101
110
111
Host interface
Generic control, data, and output pin name
CS
,
ACK
,
DS
, R/
W
,
AS
, A[4:0], D[7:0],
INT
CS
, RDY,
WR
,
RD
, ALE, A[4:0], D[7:0],
INT
CS
,
ACK
,
DS
, R/
W
,
AS
, AD[7:0],
INT
CS
, RDY,
WR
,
RD
, ALE, AD[7:0],
INT
Non-multiplexed Motorola interface
Non-multiplexed Intel interface
Multiplexed Motorola interface
Multiplexed Intel interface
TABLE - 10. PARALLEL HOST INTERFACE PINS
Figure - 16. Serial Host Mode Timing
NOTE:
1. While R/
W
=1, read from IDT82V2058; While R/
W
=0, write to IDT82V2058.
2. Ignored.
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