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| 型號： | IBM25CPC710AB3A100 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Dual Bridge and Memory Controller(IBM雙橋和存儲器控制器（連接帶同步動態(tài)RAM存儲器的Power PC 60x總線和兩個PCI端口）) |
| 中文描述： | IBM的雙橋和內(nèi)存控制器（IBM的雙橋和存儲器控制器（連接帶同步動態(tài)RAM的存儲器的Power PC處理器60倍的PCI總線和兩個端口）） |
| 文件頁數(shù)： | 207/224頁 |
| 文件大小： | 3278K |
| 代理商： | IBM25CPC710AB3A100 |
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IBM25CPC710AB3A100
IBM Dual Bridge and Memory Controller
dbamc01_ch5.fm.01
July 13, 2000
Page 195 of 208
7.3 DMA Procedure
The DMA transfer process begins when the 60x logic detects an ecowx or eciwx transaction on the processor
bus. If the RID bits in the IBM25CPC710AB3A100 and System Control register match the RID bits on the
SYS_TBST and SYS_TSIZ[0:2] lines, the 60x logic accepts the transfer. If the instruction is an ecowx, the
60x logic SYS_TAs the bus for dummy write data and sends a DMA Transfer Write command to the DMA
Controller.
The internal address bus associated with the Transfer Write command contains the address from the
processor bus. This address is placed in the XTAR register by the DMA Controller. During the processor
address tenure, the 60x logic sets an internal flag to indicate special handling of TLBSYNC operations on the
processor bus. If the flag is not set, the 60x logic ignores all TLBSYNC operations on the processor bus. If the
flag is set, a TLBSYNC operation on the bus causes the 60x logic to place a one cycle pulse on the
UX6_TLB_SYNC line to the DMA Controller. The 60x logic continuously SYS_ARTRYs the TLBSYNC bus
operation until it receives a one cycle pulse on the internal UXI_XFER_DONE line from the DMA Controller.
This pulse also resets the 60x logic
’
s internal flag to perform special handling of the TLBSYNC operations.
Note:
Since the PowerPC601 processor does not issue TLBSYNC operations, the 60x logic must treat any
SYNCs following a TLBI as a TLBSYNC operation when operating with a PowerPC601 processor.
When the eciwx instruction is used, the 60x logic performs the same steps except that the 60x logic internally
sends a DMA Transfer Read command to the DMA Controller and waits for a dummy read data response.
The dummy read data is then placed on the processor bus to complete the eciwx transfer on the processor
bus. The internal flag for special handling of TLBSYNC is set during the eciwx address bus tenure on the
processor bus.
After the DMA Controller receives the DMA Transfer command, it issues a Load Pointer command on the
internal command bus to the appropriate PCI bus bridge logic unit. This transfers the address in XPAR to the
PCI bus bridge pointer register. The DMA Controller then issues a series of Blit commands, or internal
Elementary Commands from the DMA Controller to the PCI logic, to the same PCI bus bridge logic unit that
transfers the data. The first Blit command contains the memory address stored in the XTAR register.
The PCI bus bridge logic receives the Blit commands and then executes the transfer. For Blit Reads, the
DMA Controller first determines whether the read from memory requires a snoop transaction. If the read is
coherent, the controller issues a snoop command to the 60x logic. If the snoop fails, the controller retries the
snoop until it passes. Once the snoop passes, a Blit Read command is transmitted to the PCI bus bridge
logic. The PCI Bridge logic executes the command and then increments the value in its pointer register by the
size of the transfer unless the Address Increment field in the Load Pointer command is set to No Increment.
Blit Write commands are handled in same way except the transfer is from I/O to System Memory.
Note:
The DMA Controller should wait a minimum of eight cycles before reissuing snoop commands after a
snoop fail response.
After the transfer is complete, the controller signals the 60x logic by activating UXI_XFER_DONE for one
cycle. The controller then issues a Write with Kill to the address specified in XWAR register to indicate to soft-
ware that the transfer is complete. The controller issues a Kill Cache to the 60x logic, and upon receiving a
clean response, issues a Write command to system memory. The write to memory need only be a single beat
write to the bytes reserved for DMA transfer status.
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