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| 型號： | IBM25CPC710AB3A100 |
| 廠商： | IBM Microeletronics |
| 英文描述： | IBM Dual Bridge and Memory Controller(IBM雙橋和存儲器控制器（連接帶同步動(dòng)態(tài)RAM存儲器的Power PC 60x總線和兩個(gè)PCI端口）) |
| 中文描述： | IBM的雙橋和內(nèi)存控制器（IBM的雙橋和存儲器控制器（連接帶同步動(dòng)態(tài)RAM的存儲器的Power PC處理器60倍的PCI總線和兩個(gè)端口）） |
| 文件頁數(shù)： | 168/224頁 |
| 文件大小： | 3278K |
| 代理商： | IBM25CPC710AB3A100 |
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IBM25CPC710AB3A100
IBM Dual Bridge and Memory Controller
Page 156 of 208
dbamc01_ch4.fm.01
July 13, 2000
4.7 SYNC and EIEIO
When a processor executes a SYNC instruction, a SYNC address-only tenure is broadcast on the 60x bus to
notify the system that a software-placed barrier is present. The system is responsible for ensuring all previ-
ously executed load and store operations are complete and all resultant actions are visible to the system. The
device satisfies this requirement by SYS_ARTRYing the SYNC operation until all of its store buffers are
empty, all reads have been executed, and all data have been placed in internal device buffers for requests
issued by the same processor issuing SYNC.
When a processor broadcasts an EIEIO on the 60x bus, the system is responsible for ensuring all previous
transactions are complete before executing operations. The device does not SYS_ARTRY the EIEIO
because the 60x logic dispatches bus transactions to the logic units in the order in which they occur on the
system bus and each logic unit executes its commands in the order received. For diagnostic purposes, the
device can be programmed to SYS_ARTRY the EIEIO in the same manner as SYNC.
The logic units are system memory, PCI-32 bus bridge, PCI-64 bus bridge, system I/O logic, and DMA
controller logic. EIEIO operations are valid for transfers to and from the same logic unit, but execution order of
load and store operations to different logic units cannot be guaranteed. For example, a store to the PCI-32
bus bridge followed by a PCI-64 store could be presented to the respective PCI buses in reverse order if a
bus is busy. To preserve the order among logic units, software must issue a SYNC instead of an EIEIO.
4.8 Address Retry (SYS_ARTRY)
4.8.1 Precharging SYS_ARTRY and SYS_SHD
The IBM25CPC710AB3A100 device always precharges SYS_ARTRY and SYS_SHD. All other devices on
the 60x bus must disable their precharges of these signals. The device negates SYS_ARTRY and SYS_SHD
for a half bus cycle during the second cycle following the SYS_ARTRY window
’
s last cycle.
4.8.2 SYS_ARTRY
Assertions
The device asserts SYS_ARTRY for:
SYNC operations as described in the previous section
EIEIO operations as described in the previous section
XFERDATA when more than two transfers have been initiated
a processor access to the PCI bus when a PCI-ISA bus bridge requests the same PCI bus
a processor access to system memory when a DMA occurs to the same cache line
a processor access to system memory when a DMA operation occurs to the same line
a processor access into a range of PCI-32 or PCI-64 addresses defined as potential deadlock
4.8.3 Recommended SYS_ARTRY Procedure
A master that has had its address tenure retried should negate its SYS_BR[n] for at least one bus cycle in
the cycle immediately following detection of an active SYS_ARTRY.
A master that has retried an address tenure due to a snoop hit should activate its SYS_BR[n] in the cycle
immediately following the detection of an active SYS_ARTRY. This ensures the master that retries is ser-
viced before the master that was retried.
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