參數(shù)資料
型號： IBM025171
廠商： IBM Microeletronics
英文描述： 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM)
中文描述： 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存）
文件頁數(shù)： 7/65頁
文件大?。?/td> 841K
代理商： IBM025171
IBM025160
IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
33G0307
SA14-4751-05
Revised 3/98
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 65
Truth Table
MNE Code
RE
CE
Address
DQ
0
- DQ1
5
Function
CE
TRG
W
DSF
DSF
RE
CE
RE
CE, W
CBR
0(5)
X
1(4)
0
-
X
-
X
-
CE before RE Refresh
(RESET) (9)
CBRS
0(5)
X
0(3)
1
-
STOP(6)
Point
-
X
-
CE Before RE Refresh
stop point set (2)
CBRN
0(5)
X
1(4)
1
-
X
-
X
-
CE Before RE Refresh
without mode reset
(10)
ROR
1
1
X
0
-
Row(1)
-
X
-
RE Only Refresh (11)
1
1
1
X
-
Row(1)
-
X
-
LCR
1
1
1(4)
1
1
Row(1)
X
X
Color
Load Color Register
LMR
1
1
1(4)
1
0
Row(1)
X
X
Mask
Load Mask Register
(13)
RW
1
1
1(4)
0
0
Row
Column
X
Valid
Data
Input
Read/Write Cycle (No
Mask)
RWM
1
1
0(3)
0
0
Row
Column
WPBM
(7)
Valid
Data
Input
Read/Write Cycle
(Masked)
BW
1
1
1(4)
0
1
Row
Column
A3-A8
X
Column
mask
Block Write Cycle (No
Mask)
BWM
1
1
0(3)
0
1
Row
Column
A3-A8
WPBM
(7)
Column
mask
Block Write Cycle
(Masked)
FWM
1
1
0(3)
1
X
Row
X
WPBM
(7)
X
Flash Write Cycle
(Masked) (8)
RT
1
0
1(4)
0
X
Row
TAP
X
X
Full - Register Read
Transfer
MWT
1
0
0(3)
0
X
Row
TAP (12)
WPBM
(7)
X
Masked Full - Register
Write Transfer
SRT
1
0
1(4)
1
X
Row
TAP
X
X
Split Read Transfer
MSWT
1
0
0(3)
1
X
Row
TAP
WPBM
(7)
X
Masked Split Write
Transfer
1. Row address needed only for refresh operation to the selected row. Otherwise this is a don’t care.
2. This cycle is used to put the chip into special modes. The Address at RE fall becomes the Serial port STOP address. CBRS
cycle(s) should be performed immediately after the power up initialization cycles.
3. Either W is 0.
4. Both W are 1.
5. Either CE is 0 on Dual CE parts.
6. STOP defines the Serial port address on which shift out moves to the other half of the SAM.
7. After LMR, WPBM is only changed by LMR. CBR resets the persistent mask.
8. No byte select, both bytes are written.
9. CBR mode will reset all the unknown modes at power up. It will also clear persistent Write-per-Bit mode.
10. CBRN mode will not clear persistent Write-per-Bit mode.
11. ROR will not clear inadvertent modes at power up time.
12. A
0
-A
7
define the tap point for the Serial Data input after the transfer. A
8
defines the particular half of the DRAM row in which the
SAM data will be transferred.
13. LMR cycle will set the persistent Write-per-Bit mode. The persistent Write-per-Bit mode is reset by CBR cycle only.
14. DQ
0
- DQ
15
are latched on either the first WEX falling edge or the falling edge of CAS, whichever occurs later.
Legend:
‘X’ = Don’t Care; ‘-’ = Not Applicable
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