
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
IBM025160
IBM025161
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 65
33G0307
SA14-4751-05
Revised 3/98
Serial Read, Write and Transfer Cycle
Symbol
Parameter
-6H
-60
-70
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
CSD
CE low to first SC high after TRG goes high
15
—
15
—
17
—
ns
t
CTH
Delay time from CE low to TRG high
15
—
15
—
15
—
ns
t
d(RHMS)
Delay time, RE high to last (most significant rising
edge of SC before boundary switch during split read
transfer Cycles
20
—
20
—
20
—
ns
t
DTH
TRG hold after RE high
5
—
5
—
5
—
ns
t
d(TPRL)
Delay time, first (TAP) rising edge of SC after bound-
ary switch to RE low during split read transfer cycles
15
—
15
—
17
—
ns
t
ESR
SE setup before RE low
0
—
0
—
0
—
ns
t
RSD
RE low to first SC high after TRG goes high
60
—
60
—
70
—
ns
t
RTH
RE low to TRG high
45
—
45
—
55
—
ns
t
SC
Width of SC high
4
—
6
—
7
—
ns
t
SCA
Access time from SC going high
3
12
3
15
3
17
ns
1
t
SCC
Serial clock cycle time
12
—
18
—
20
—
ns
t
SCP
Width of SC low
4
—
6
—
7
—
ns
t
SDH
Serial data-in hold time after SC high
5
—
5
—
5
—
ns
t
SDS
Serial data-in setup time to SC high
2
—
2
—
2
—
ns
t
SEA
Access time from SE going low
—
10
—
12
—
15
ns
t
SFD
Serial enable setup time to SC high
3
—
3
—
3
—
ns
t
SEZ
Serial output disable from SE high
0
8
0
8
0
10
ns
t
SOH
Old Serial data out hold time after SC high
3
—
3
—
3
—
ns
t
SRS
SC going high to RE low
8
—
8
—
10
—
ns
t
SWS
TRG high to SC high (first serial clock after real time
transfer)
8
—
8
—
10
—
ns
t
TCH
TRG hold time to CE high
8
—
8
—
10
—
ns
t
TRH
TRG hold to RE high
8
—
8
—
10
—
ns
t
TRP
RE high to SC high (Serial write transfer)
15
—
15
—
20
—
ns
t
TSL
SC high delay to TRG high during a real time read
transfer
5
—
5
—
5
—
ns
1. Measured with the specified current and 30 pF load for the Serial port. Output referenced levels: V
OH
= 2.0V and V
OL
= 0.8V.