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| 型號： | IBM025171 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM) |
| 中文描述： | 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存） |
| 文件頁數(shù)： | 55/65頁 |
| 文件大?。?/td> | 841K |
| 代理商： | IBM025171 |
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IBM025160
IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
33G0307
SA14-4751-05
Revised 3/98
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 55 of 65
Split Register Write Transfer (Normal) Mode
The Split Write Transfer is used to write data continuously in the Serial port without having to worry about
synchronizing the SC clock with the operation of the primary port. This transfer operation stores 128x16 bits
from SAM in the selected row segment. CA
8
at CE fall time during a Split Write Transfer cycle determines to
which half of the row the data from SAM is going to be stored.
CA
7
is a don't care and is internally gener-
ated based on which half of the SAM is active
. This way, the data from the idle part of SAM can be trans-
ferred to the selected row in DRAM while the new data is being written in the active half of SAM. The start
address is given by CA
6
-CA
0
but is held in the TAP address register until the Serial port counter reaches the
jump address. At that point, the start address register is loaded with the address from the TAP address regis-
ter and the Serial port counter will also be loaded with this address at the same time. The writing of data in the
previous inactive half of SAM will start at this address at the next SC clock. The Split Write Transfer in normal
mode is illustrated in the timing diagram on page 45.
The example in the timing diagram on page 56 illustrates a Split Write Transfer between SAM and DRAM
based on user supplied address CA
8
at CE fall during transfer cycle and an internally generated CA
7
. In the
first example, the Serial port is active writing data in the upper half of the SAM while the lower half of SAM is
idling. Therefore, CA
7
is internally changed to “0” and the transfer is forced to lower quarter of the upper half
of the selected row based on CA
8
= 1. In the second example, user supplies bit CA
8
is “1” and the Serial port
is active writing data in the lower half of SAM, the transfer is therefore forced to the uppermost quarter of the
selected row.
Note: A Full Write Transfer with WPBM must be performed before the start of any Split Write Trans-
fer. After the Full Write Transfer, any number of Split Write Transfers can be performed. The Split
Write Transfer can be initiated from the idling part of SAM at any time while the active half is being
written. It is generally a good practice to perform a Split Write Transfer from the idle half of the SAM at
any time which is way ahead of the last data being written into the active half of the SAM.
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