參數(shù)資料
型號(hào)： IBM025171
廠商： IBM Microeletronics
英文描述： 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM)
中文描述： 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存）
文件頁(yè)數(shù)： 58/65頁(yè)
文件大小： 841K
代理商： IBM025171
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
IBM025160
IBM025161
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 58 of 65
33G0307
SA14-4751-05
Revised 3/98
The example illustrates a full transfer in SRS mode based on CA
7
=1.
Split Register Read Transfer (SRS) Mode
The Split Read Transfer in SRS mode is used to read data continuously from the Serial port without synchro-
nizing the SC clock with the operation of the primary port. This mode is most useful for tiling applications. It is
also used to make Half depth SAM VRAM parts compatible to Full depth SAM VRAM parts. When the Split
Read Transfer in SRS mode is invoked, 128 x16 bits are transferred from a selected row based on user sup-
plied column address “CA
7
” at CE fall time and the Serial port counter reading. For example if the upper half
of SAM is being read and user supplied CA
7
is “1”, then the data having physical addresses “CA
7
=1 and CA
8
= 0" from the selected row is transferred to the lower half of SAM. If the lower half of SAM is being read and
the user supplied column address CA
7
is “1”, the data having physical addresses “CA
7
= 1 and CA
8
=1” from
the selected row is transferred to the upper half of SAM. This is illustrated in the timing diagram on page 59.
The user supplied column address “CA
6
- CA
0
” is held in a TAP address register until the Serial port counter
reaches the STOP address. At that point, the start address register is loaded with the contents of the TAP
address register. The Serial port counter is updated with this address at the same time. The reading of data
from the Serial port will commence from this address in the previously inactive half of SAM at the next SC
clock.
Full Register Read Transfer (SRS) Mode
Array
511
Rows
Cols
SAM
0
127
128
255
0
383
511
255
127
CA
7
=0 CA
8
=0
CA
7
=1 CA
8
=0
CA
7
=0 CA
8
=1
CA
7
=1 CA
8
=1
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