參數(shù)資料
型號(hào)： IBM025171
廠商： IBM Microeletronics
英文描述： 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM)
中文描述： 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存）
文件頁數(shù)： 49/65頁
文件大小： 841K
代理商： IBM025171
IBM025160
IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
33G0307
SA14-4751-05
Revised 3/98
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 49 of 65
Block Write Operation
The Block Write Cycles are useful for clearing windows and for accelerating polygon fill operations. In all
Block Write operations, the data is always supplied by the color register which is loaded by invoking a Load
Color Register operation prior to the Block Write cycle(s). The color register data bits can individually be
masked by either loading the mask at RE fall time (non-persistent mask) provided that no Load Mask Regis-
ter operation has been performed prior to invoking Block Write cycle(s). If a Load Mask Register operation
has been performed and W is low at RE fall time, WPBM mask at RE time will be ignored and the mask from
the Mask Register (persistent mask) will be applied to the color data bits during Block Write cycle(s).
lower or
upper or both bytes can be written during Block Write cycle(s)
. Also a feature known as “individual Col-
umn masking” can be used to mask all or any of the 8 columns by loading the column mask at DQ pins at CE
fall time. This operation is illustrated in and the Application Note, “8 Column Block Write”.
For example, if DQ
0
is “0”, mask the lower byte of column 1 in the block. If DQ
8
is “1”, write in the upper byte
of column 1
1L = Lower byte of column 1.
1U = Upper byte of column 1.
Block Write (No Mask)
The data from the color register is written to any or all of the eight columns starting with the column address
A
8
-A
3
(A
2
, A
1
, A
0
are don't care). Any column or columns in a block of 8 columns can be masked by latching
the DQ data at CE fall time during Block Write page cycles in a way as illustrated in the timing diagram on
page 33.
Both W should be kept high at RE fall time so that no mask is used at Block Write cycle time
.
Block Write (Non-persistent Mask)
The WPBM is loaded by bringing W low at RE fall time and latching the data present at DQ pins. This mask is
applied to the data from Color Register during Block Write page cycles. Note that the masked data is written
to all or any of the non-masked columns in the selected block. The WPBM so latched at RE fall time is appli-
cable during that particular RE active cycle time only.
Block Write (Persistent Mask or Old Mask)
An LMR cycle is initiated to load the Mask Register prior to executing a Block Write operation with persistent
mask. The 16-bit Mask Register supplies the bit mask for color register data during page mode Block Write
cycles. This masked data is then written to all or any of the non-masked columns in the 8-column block.
W is
low at RE time and any data on DQ pins at RE fall time will be ignored. To clear the persistent mask, a
CBR cycle is initiated
.
DQ data at CE fall time during Block Write cycle(s)
DQ
i
= 0, Mask the selected column in the block
DQ
i
= 1, Write the data in the selected column in the block
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
1L
2L
3L
4L
5L
6L
7L
8L
1U
2U
3U
4U
5U
6U
7U
8U
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