參數(shù)資料
型號: HYB18L256160BF-7.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: RT ANG PCB CONT .40/1.295 BULK
中文描述: BJAWBMSpecialty DRAM的移動RAM
文件頁數(shù): 39/49頁
文件大?。?/td> 1327K
代理商: HYB18L256160BF-7.5
Data Sheet
39
V1.4, 2004-04-30
HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.10
POWER DOWN
Figure 45
Power Down Entry Command
Power-down is entered when CKE is registered LOW
(no accesses can be in progress). If power-down
occurs when all banks are idle, this mode is referred to
as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred
to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CLK
and CKE. CKE LOW must be maintained during power-
down.
Power-down duration is limited by the refresh
requirements of the device (
t
REF
).
The power-down state is synchronously exited when
CKE is registered HIGH (along with a NOP or
DESELECT command). One clock delay is required for
power down entry and exit.
Figure 46
Power Down Entry and Exit
2.4.10.1
The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current
consumption. Deep power down mode is entered using the BURST TERMINATE command (cf.
Figure 35
) except
that CKE is LOW. All internal voltage generators inside the device are stopped and all memory data is lost in this
mode. To enter the deep power down mode all banks must be precharged.
The deep power down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command
sequence as for power-up initialization, including the 200μs initial pause, has to be applied before any other
command may be issued (cf.
Figure 3
and
Figure 4
).
DEEP POWER DOWN
= Don't Care
CS
CKE
CLK
RAS
A0-A12
BA0,BA1
WE
CAS
= Don't Care
Precharge Power Down mode shown: all banks are idle and tRP met
when Power Down Entry Command is issued
Any
Command
Power Down
Entry
t
RP
Exit from
Power Down
High-Z
DQ
A10 (AP)
Valid
Pre All
Address
Valid
Command
NOP
NOP
NOP
Valid
PRE
CKE
CLK
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