參數(shù)資料
型號(hào): HYB18L256160BF-7.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: RT ANG PCB CONT .40/1.295 BULK
中文描述: BJAWBMSpecialty DRAM的移動(dòng)RAM
文件頁(yè)數(shù): 20/49頁(yè)
文件大?。?/td> 1327K
代理商: HYB18L256160BF-7.5
HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Functional Description
Data Sheet
20
V1.4, 2004-04-30
2.4.4
ACTIVE
Figure 9
ACTIVE Command
Before any READ or WRITE commands can be issued
to a bank within the
Mobile-RAM
, a row in that bank
must be “opened” (activated). This is accomplished via
the ACTIVE command and addresses A0 - A12, BA0
and BA1 (see
Figure 9
), which decode and select both
the bank and the row to be activated. After opening a
row (issuing an ACTIVE command), a READ or WRITE
command may be issued to that row, subject to the
t
RCD
specification. A subsequent ACTIVE command to a
different row in the same bank can only be issued after
the
previous
active
row
(precharged).
The minimum time interval between successive
ACTIVE commands to the same bank is defined by
t
RC
.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE
commands to different banks is defined by
t
RRD
.
has
been
“closed”
Figure 10
Bank Activate Timings
= Don't Care
BA = Bank Address
RA = Row Address
BA0,BA1
BA
A0-A12
RA
WE
CAS
RAS
CS
CKE
(High)
CLK
Table 9
Parameter
Timing Parameters for ACTIVE Command
Symbol
- 7.5
Units
Notes
min.
67
19
15
max.
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
t
RC
t
RCD
t
RRD
ns
ns
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
1)
1)
t
RRD
t
RCD
= Don't Care
CLK
RD/WR
NOP
NOP
NOP
ACT
NOP
ACT
Command
ROW
ROW
COL
A0-A12
BA x
BA y
BA y
BA0, BA1
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