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參數(shù)資料
| 型號： | HYB18L256160BF-7.5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | RT ANG PCB CONT .40/1.295 BULK |
| 中文描述： | BJAWBMSpecialty DRAM的移動RAM |
| 文件頁數(shù)： | 12/49頁 |
| 文件大?。?/td> | 1327K |
| 代理商： | HYB18L256160BF-7.5 |
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HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Functional Description
Data Sheet
12
V1.4, 2004-04-30
1. At first, device core power (
V
DD
) and device IO power (
V
DDQ
) must be brought up simultaneously. Typically
V
DD
and
V
DDQ
are driven from a single power converter output.
Assert and hold CKE and DQM to a HIGH level.
2. After
V
DD
and
V
DDQ
are stable and CKE is HIGH, apply stable clocks.
3. Wait for 200μs while issuing NOP or DESELECT commands.
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least
t
RP
period.
5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least
t
RFC
period.
6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode
Register, each followed by NOP or DESELECT commands for at least
t
MRD
period; the order in which both
registers are programmed is not important.
Following these steps, the Mobile-RAM is ready for normal operation.
2.2
Register Definition
2.2.1
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes
the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst
mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it is programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Mode Register
MR
Mode Register Definition
(BA[1:0] = 00
B
)
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
WB
0
0
CL
BT
BL
Field
WB
Bits
9
Type
w
Description
Write Burst Mode
0
Burst Write
1
Single Write
CAS Latency
010 2
011 3
Note:All other bit combinations are RESERVED.
Burst Type
0
Sequential
1
Interleaved
Burst Length
000 1
001 2
010 4
011 8
111 full page (Sequential burst type only)
Note:All other bit combinations are RESERVED.
CL
[6:4]
w
BT
3
w
BL
[2:0]
w
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18L256160BFL-7.5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:DRAMs for Mobile Applications 256-Mbit Mobile-RAM |
| HYB18L256160BFX-7.5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:DRAMs for Mobile Applications 256-Mbit Mobile-RAM |
| HYB18L2561660BF-7.5 | 制造商:QIMONDA 功能描述: |
| HYB18L256169BF | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Mobile-RAM |
| HYB18L256169BF-7.5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Mobile-RAM |
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