參數(shù)資料
型號: HYB18L256160BF-7.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: RT ANG PCB CONT .40/1.295 BULK
中文描述: BJAWBMSpecialty DRAM的移動(dòng)RAM
文件頁數(shù): 22/49頁
文件大?。?/td> 1327K
代理商: HYB18L256160BF-7.5
HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Functional Description
Data Sheet
22
V1.4, 2004-04-30
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 13
and
Figure 14
show single READ bursts for each supported CAS latency setting.
Figure 13
Single READ Burst (CAS Latency = 2)
Table 10
Parameter
Timing Parameters for READ
Symbol
- 7.5
Units
Notes
min.
1.0
3.0
2.5
67
19
45
19
max.
5.4
6.0
7.0
2
100k
Access time from CLK
CL = 3
CL = 2
t
AC
t
AC
t
LZ
t
HZ
t
OH
t
DQZ
t
RC
t
RCD
t
RAS
t
RP
ns
ns
ns
ns
ns
t
CK
ns
ns
ns
ns
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
PRECHARGE command period
1)
1)
1)
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Ba A, Col n = bank A, column n
DO n = Data Out from column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n.
= Don't Care
CL=2
t
RCD
t
RAS
t
RC
t
RP
CLK
Command
NOP
READ
NOP
NOP
NOP
PRE
NOP
ACT
ACT
Address
Ba A,
Row b
Ba A,
Col n
Ba A,
Row x
A10 (AP)
Pre Bank A
Pre All
Dis AP
Row x
Row b
AP
DO n+1
DO n
DO n+2
DO n+3
DQ
AP = Auto Precharge
Dis AP = Disable Auto Precharge
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