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參數(shù)資料
| 型號： | HM5212805DLTD-10 |
| 元件分類： | DRAM |
| 英文描述： | 16M X 8 SYNCHRONOUS DRAM, 8 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 51/53頁 |
| 文件大小： | 552K |
| 代理商： | HM5212805DLTD-10 |
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HM5212165D Series, HM5212805D Series
7
Pin Functions
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK
rising edge.
CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS and WE (input pins): Although these pin names are the same as those of conventional
DRAMs, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CLK rising edge.
Column address (AY0 to AY8; HM5212165D, AY0 to AY9;
HM5212805D) is determined by A0 to A8 or A9 (A8; HM5212165D, A9; HM5212805D) level at the read
or write command cycle CLK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are
precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by
A12/A13 (BS) is precharged. For details refer to the command operation section.
A12/A13 (input pin): A12/A13 are bank select signal (BS). The memory array of the HM5212165D, the
HM5212805D is divided into bank 0, bank 1, bank 2 and bank 3. HM5212165D contain 4096-row
× 512-
column
× 16-bit. HM5212805D contain 4096-row × 1024-column × 8-bit. If A12 is Low and A13 is Low,
bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High,
bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected.
CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next
CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-
down mode, clock suspend mode and self refresh mode.
DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers.
Read operation: If DQM, DQMU/DQML is High, the output buffer becomes High-Z. If the DQM,
DQMU/DQML is Low, the output buffer becomes Low-Z. (The latency of DQM, DQMU/DQML during
reading is 2 clocks.)
Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written).
If DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing
is 0 clock.)
DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5212165D,
DQ0 to DQ7; HM5212805D).
V
CC and VCCQ (power supply pins): 3.3 V is applied.
(V
CC is for the internal circuit and VCCQ is for the
output buffer.)
V
SS and VSSQ (power supply pins):
Ground is connected. (V
SS is for the internal circuit and VSSQ is for
the output buffer.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5212805FLTD-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
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