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| 型號(hào)： | HM5212805DLTD-10 |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 16M X 8 SYNCHRONOUS DRAM, 8 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 33/53頁(yè) |
| 文件大小： | 552K |
| 代理商： | HM5212805DLTD-10 |
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HM5212165D Series, HM5212805D Series
39
AC Characteristics (Ta = 0 to 70C, V
CC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
HM5212165D/HM5212805D-
10
Parameter
Symbol
Min
Max
Unit
Notes
System clock cycle time (
CAS latency = 2)
t
CK
15
—
ns
1
CLK high pulse width
t
CKH
3
—
ns
1
CLK low pulse width
t
CKL
3
—
ns
1
Access time from CLK (
CAS latency = 2)
t
AC
—
8
ns
1, 2
Data-out hold time
t
OH
2.5
—
ns
1, 2
CLK to Data-out low impedance
t
LZ
2
—
ns
1, 2, 3
CLK to Data-out high impedance
t
HZ
—
7
ns
1, 4
Data-in setup time
t
DS
2.5
—
ns
1
Data in hold time
t
DH
1.5
—
ns
1
Address setup time
t
AS
2.5
—
ns
1
Address hold time
t
AH
1.5
—
ns
1
CKE setup time
t
CES
2.5
—
ns
1, 5
CKE setup time for power down exit
t
CESP
2.5
—
ns
1
CKE hold time
t
CEH
1.5
—
ns
1
Command (
CS, RAS, CAS, WE, DQM) setup
time
t
CS
2.5
—
ns
1
Command (
CS, RAS, CAS, WE, DQM) hold time t
CH
1.5
—
ns
1
Ref/Active to Ref/Active command period
t
RC
90
—
ns
1
Active to Precharge command period
t
RAS
60
120000
ns
1
Active command to column command
(same bank)
t
RCD
30
—
ns
1
Precharge to active command period
t
RP
30
—
ns
1
Write recovery or data-in to precharge lead time
t
DPL
15
—
ns
1
Active (a) to Active (b) command period
t
RRD
20
—
ns
1
Transition time (rise to fall)
t
T
15ns
Refresh period
t
REF
—64
ms
Notes: 1. AC measurement assumes t
T = 1 ns.
Reference level for timing of input signals is 1.4 V.
2. Access time is measured at 1.4 V. Load condition is CL = 50 pF with current source.
3. t
LZ (max) defines the time at which the outputs achieves the low impedance state.
4. t
HZ (max) defines the time at which the outputs achieves the high impedance state.
5. t
CES define CKE setup time to CLK rising edge except power down exit command.
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| HM5212805FLTD-75 | 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-A60 | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-B60 | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-75 | 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-A60 | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
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