參數(shù)資料
型號(hào): HM5212805DLTD-10
元件分類: DRAM
英文描述: 16M X 8 SYNCHRONOUS DRAM, 8 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁(yè)數(shù): 22/53頁(yè)
文件大?。?/td> 552K
代理商: HM5212805DLTD-10
HM5212165D Series, HM5212805D Series
29
Read command to Precharge command interval (same bank):
When the precharge command is executed for the same bank as the read command that preceded it, the
minimum interval between the two commands is one clock. However, since the output buffer then
becomes High-Z after the clocks defined by l
HZP, there is a case of interruption to burst read data output will
be interrupted, if the precharge command is input during burst read. To read all data by burst read, the
clocks defined by l
EP must be assured as an interval from the final data output to precharge command
execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CAS Latency = 2, Burst Length = 4
CLK
Command
Dout
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=2
l
= -1 cycle
EP
READ to PRECHARGE Command Interval (same bank): To stop output data
CAS Latency = 2, Burst Length = 1, 2, 4, 8, full page burst
CLK
Command
Dout
READ
PRE/PALL
out A0
lHZP =2
High-Z
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5212805FLTD-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM
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HM5212805FLTD-B60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
HM5212805FTD-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM
HM5212805FTD-A60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM