參數(shù)資料
型號: HM5212805DLTD-10
元件分類: DRAM
英文描述: 16M X 8 SYNCHRONOUS DRAM, 8 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 32/53頁
文件大?。?/td> 552K
代理商: HM5212805DLTD-10
HM5212165D Series, HM5212805D Series
38
Notes: 1. I
CC depends on output load condition when the device is selected.
I
CC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
9. Input signals are V
IH or VIL fixed.
Capacitance (Ta = 25
°C, V
CC, VCCQ = 3.3 V ± 0.3 V)
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
C
I1
7
pF
1, 2, 4
Input capacitance (Signals)
C
I2
7
pF
1, 2, 4
Output capacitance (DQ)
C
O
8
pF
1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQM, DQMU/DQML = V
IH to disable Dout.
4. This parameter is sampled and not 100% tested.
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