參數(shù)資料
型號: HM5212805DLTD-10
元件分類: DRAM
英文描述: 16M X 8 SYNCHRONOUS DRAM, 8 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 20/53頁
文件大?。?/td> 552K
代理商: HM5212805DLTD-10
HM5212165D Series, HM5212805D Series
27
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of
the same bank as the preceding read command, the write command can be performed after an interval of no
less than 1 clock. However, DQM, DQMU/DQML must be set High so that the output buffer becomes
High-Z before data input.
READ to WRITE Command Interval (1)
CLK
Command
Dout
in B2
in B3
READ WRIT
in B0
in B1
High-Z
Din
CL=2
DQM,
DQMU
/DQML
Burst Length = 4
Burst write
READ to WRITE Command Interval (2)
CLK
Command
Dout
READ
WRIT
Din
CL=2
DQM,
DQMU/DQML
High-Z
2 clock
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no
less than 1 clock, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML
must be set High so that the output buffer becomes High-Z before data input.
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參數(shù)描述
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HM5212805FLTD-B60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM
HM5212805FTD-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM
HM5212805FTD-A60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM