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FLER bit setting conditions are as follows:
When flash memory is read during programming/erasing (including a vector read or
instruction fetch)
Immediately after exception handling (excluding a reset) during programming/erasing
When a SLEEP instruction (transition to software standby, sleep, subactive, subsleep, or
watch mode) is executed during programming/erasing
When the bus is released during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 21.14 shows the flash memory state transition diagram.
RD VF PR ER FLER = 0
Error
occurrence*1
RES = 0 or STBY = 0
RES = 0 or
STBY = 0
RD VF PR ER FLER = 0
Program mode
Erase mode
Reset or hardware standby
(hardware protection)
RD VF*4
PR ER FLER = 1
RD VF PR ER FLER = 1
Error protection mode
Error protection
mode (software standby,
sleep, subsleep, and watch )
Software standby,
sleep, subsleep, and
watch mode
FLMCR1, FLMCR2 (except
FLER bit), EBR1, EBR2
initialization state*3
FLMCR1,
FLMCR2,
EBR1, EBR2
initialization
state
Software standby,
sleep, subsleep, and
watch mode release
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Legend:
RES = 0 or
STBY = 0
Error occurrence*2
Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is
executed for a transition to subactive mode
2. When an error occurs due to a SLEEP instruction (except subactive mode)
3. Except sleep mode
4.
VF in subactive mode
Figure 21.14 Flash Memory State Transitions