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391
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor
interrupts. The MPIE bit setting is only valid in asynchronous mode when receiving with the MP
bit in SMR set to 1.
The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupts disabled (normal reception performed)
(Initial value)
[Clearing conditions]
When the MPIE bit is cleared to 0
When data with MPB = 1 is received
1
Multiprocessor interrupts enabled*
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR,
receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not
performed. When receive data with MPB = 1 is received, the MPB bit in SSR is set to 1,
the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when
the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt
(TEI) request generation if there is no valid transmit data in TDR when the MSB is transmitted.
Bit 2
TEIE
Description
0
Transmit-end interrupt (TEI) request disabled*
(Initial value)
1
Transmit-end interrupt (TEI) request enabled*
Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing
it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.