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8
1.2
Internal Block Diagram
An internal block diagram of the H8S/2138 Series is shown in figure 1.1, and an internal block
diagram of the H8S/2134 Series in figure 1.2.
H8S/2000 CPU
DTC
WDT0, WDT1
ROM
RAM
P17/A7/PW7
P16/A6/PW6
P15/A5/PW5
P14/A4/PW4
P13/A3/PW3
P12/A2/PW2
P11/A1/PW1
P10/A0/PW0
P27/A15/PW15/CBLANK
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
P37/D7/HDB7
P36/D6/HDB6
P35/D5/HDB5
P34/D4/HDB4
P33/D3/HDB3
P32/D2/HDB2
P31/D1/HDB1
P30/D0/HDB0
P97/
WAIT/SDA0
P96//EXCL
P95/
AS/IOS/CS1
P94/
WR/IOW
P93/
RD/IOR
P92/
IRQ0
P91/
IRQ1
P90/
IRQ2/ADTRG/ECS2
P67/TMOX/CIN7/
KIN7/IRQ7
P66/FTOB/CIN6/
KIN6/IRQ6
P65/FTID/CIN5/
KIN5
P64/FTIC/CIN4/
KIN4/CLAMPO
P63/FTIB/CIN3/
KIN3/VFBACKI
P62/FTIA/CIN2/
KIN2/VSYNCI/TMIY
P61/FTOA/CIN1/
KIN1/VSYNCO
P60/FTCI/CIN0/
KIN0/HFBACKI/TMIX
P47/PWX1
P46/PWX0
P45/TMRI1/HIRQ12/CSYNCI
P44/TMO1/HIRQ1/HSYNCO
P43/TMCI1/HIRQ11/HSYNCI
P42/TMRI0/SCK2/SDA1
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
P52/SCK0/SCL0
P51/RxD0
P50/TxD0
P77/AN7/DA1
P76/AN6/DA0
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P86/
IRQ5
/SCK1/SCL1
P85/
IRQ4
/RxD1
P84/
IRQ3
/TxD1
P83
P82/HIFSD
P81/
CS2
/GA20
P80/HA0
AVCC
AVSS
RES
XTAL
EXTAL
MD1
MD0
NMI
STBY
VCC1
VCC2
VSS
Port
9
Port
6
Port
4
Port
5
Port
2
Port
1
Port
3
Clock
pulse
generator
Interrupt
controller
16-bit FRT
8-bit timer
× 4ch
(TMR0, TMR1,
TMRX, TMRY)
Timer connection
SCI
× 3ch
(IrDA
× 1ch)
IIC
× 2ch
(option)
Port 8
Port 7
Internal
data
bus
Internal
address
bus
Bus
controller
8-bit PWM
14-bit PWM
Host interface
10-bit A/D
8-bit D/A
Figure 1.1 Internal Block Diagram of H8S/2138 Series