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Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor
reads IDR2.
The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For
details see table 17.8, Fast A20 Gate Output Signals.
Bit 1
IBF
Description
0
[Clearing condition]
When the slave processor reads IDR2
(Initial value)
1
[Setting condition]
When the host processor writes to IDR2
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared
to 0 when the host processor reads ODR2. The IBF flag setting and clearing conditions are
different when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output
Signals.
Bit 0
OBF
Description
0
[Clearing condition]
When the host processor reads ODR2 or the slave writes 0 in the OBF bit
(Initial value)
1
[Setting condition]
When the slave processor writes to ODR2
Table 17.4 shows the conditions for setting and clearing the STR2 flags.
Table 17.4 Set/Clear Timing for STR2 Flags
Flag
Setting Condition
Clearing Condition
C/
'
Rising edge of host’s write signal
(
,2:) when HA0 is high
Rising edge of host’s write signal (
,2:)
when HA0 is low
IBF*
Rising edge of host’s write signal
(
,2:) when writing to IDR2
Falling edge of slave’s internal read signal
(
5') when reading IDR2
OBF
Falling edge of slave’s internal write
signal (
:5) when writing to ODR2
Rising edge of host’s read signal (
,25)
when reading ODR2
Note: * The IBF flag setting and clearing conditions are different when the fast A20 gate is used.
For details see table 17.8, Fast A20 Gate Output Signals.