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Table 7.9
Number of States Required for Each Execution Phase
Object of Access
On-
Chip RAM
On-
Chip ROM
Internal I/O
Registers
External Devices
Bus width
32
16
8
16
8
Access states
1
2223
Execution
phase
Vector read
S
I
—
1
—
4
6+2m
Register
information
read/write
S
J
1
—
————
Byte data read
S
K
1
2223+m
Word data read
S
K
1
4
2
4
6+2m
Byte data write
S
L
1
2223+m
Word data write
S
L
1
4
2
4
6+2m
Internal operation S
M
1
1111
The number of execution states is calculated from the formula below. Note that
Σ means the sum
of all transfers activated by one activation event (the number for which the CHNE bit is set to
one, plus 1).
Number of execution states = I S
I + Σ (J SJ + K SK + L SL) + M SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for
the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
7.3.11
Procedures for Using the DTC
Activation by Interrupt: The procedure for using the DTC with interrupt activation is as
follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The
DTC is activated when an interrupt used as an activation source is generated.
5. After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.