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328
Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance
with the lower 8-bit compare-match conditions.
Compare-Match Count Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts
compare-match A’s for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clearing are in accordance with
the settings for each channel.
Usage Note: If the 16-bit count mode and compare-match count mode are set simultaneously,
the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop
operating. Simultaneous setting of these two modes should therefore be avoided.
12.4
Interrupt Sources
The TMR0, TMR1, and TMRY 8-bit timers can generate three types of interrupt: compare-
match A and B (CMIA and CMIB), and overflow (OVI). TMRX can generate only an ICIX
interrupt. An interrupt is requested when the corresponding interrupt enable bit is set in TCR or
TCSR. Independent signals are sent to the interrupt controller for each interrupt. It is also
possible to activate the DTC by means of CMIA and CMIB interrupts from TMR0, TMR1 and
TMRY.
An overview of 8-bit timer interrupt sources is given in tables 12.3 to 12.5.
Table 12.3 TMR0 and TMR1 8-Bit Timer Interrupt Sources
Interrupt source
Description
DTC Activation
Interrupt Priority
CMIA
Requested by CMFA
Possible
High
CMIB
Requested by CMFB
Possible
OVI
Requested by OVF
Not possible
Low
Table 12.4 TMRX 8-Bit Timer Interrupt Source
Interrupt source
Description
DTC Activation
ICIX
Requested by ICF
Not possible