28F320D18
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71
A.5
System Interface Information
.
A.6
Device Geometry Information
This field provides critical details of the flash device geometry.
Table 18. System Interface Information
Offset
Length
Description
Address
Hex Code
Value
1Bh
1
V
logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1B:
--17
1.7 V
1Ch
1
V
logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1C:
--19
1.9 V
1Dh
1
V
[programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
1D:
--B4
11.4 V
1Eh
1
V
[programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
1E:
--C6
12.6 V
1Fh
1
“n” such that typical single word program time-out = 2
n
μs
1F:
--05
32 μs
20h
1
“n” such that typical max. buffer write time-out = 2
n
μs
20:
--00
n/a
21h
1
“n” such that typical block erase time-out = 2
n
ms
21:
--0A
1 s
22h
1
“n” such that typical full chip erase time-out = 2
n
ms
22:
--00
n/a
23h
1
“n” such that maximum word program time-out = 2
n
times typical
23:
--04
512 μs
24h
1
“n” such that maximum buffer write time-out = 2
n
times typical
24:
--00
n/a
25h
1
“n” such that maximum block erase time-out = 2
n
times typical
25:
--03
8 s
26h
1
“n” such that maximum chip erase time-out = 2
n
times typical
26:
--00
n/a
Table 19. Device Geometry Information
Offset
Length
Description
Code
27h
1
“n” such that device size = 2
n
in number of bytes
27:
See
Device
Geometry
Definition
Table
--01
--00
--00
--00
--03
28h
2
Flash device interface: x8 async x16 async x8/x16 async
28:00,29:00 28:01,29:00 28:02,29:00
“n” such that maximum number of bytes in write buffer = 2
n
28:
29:
2A:
2B:
2C:
x16
2Ah
2
0
2Ch
1
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions with
one or more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
3