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| 型號： | GT28F320D18B110 |
| 英文描述： | x16 Flash EEPROM |
| 中文描述： | x16閃存EEPROM |
| 文件頁數(shù)： | 24/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | GT28F320D18B110 |
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28F320D18
20
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Table 8. Read Configuration Register Definition
RM
R
FC2
FC1
FC0
R
DOC
WC
15
14
13
12
11
10
9
8
BS
CC
R
R
BW
BL2
BL1
BL0
7
6
5
4
3
2
1
0
NOTES:
RCR.15 = READ MODE (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
Read mode configuration affects reads from main blocks.
Parameter block, status register, and configuration reads
support single read cycles.
RCR.14 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use. Set reserved bits to “0.”
RCR.13–11 = FREQUENCY CONFIGURATION (FC2-0)
000 = Code 0 reserved for future use
001 = Code 1 reserved for future use
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5 reserved for future use
110 = Code 6 reserved for future use
111 = Code 7 reserved for future use (Default)
See
Section 4.10.2
for information about the frequency
configuration and its effect on the initial read.
Undocumented combinations of bits
RCR.14–11 are reserved by Intel Corporation for future
implementations and should not be used.
RCR.10 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use. Set reserved bits to “0.”
RCR.9 = DATA OUTPUT CONFIGURATION (DOC)
0 = Hold Data for One Clock
1 = Reserved for future use (Default)
Undocumented combinations of bits RCR.10–9 are reserved
by Intel Corporation for future implementations and should not
be used.
RCR.8 = WAIT CONFIGURATION (WC)
0 = WAIT# Asserted During Delay
1 = WAIT# Asserted One Data Cycle Before Delay (Default)
RCR.7 = BURST SEQUENCE (BS)
0 = Intel Burst Order
1 = Linear Burst Order (Default)
RCR.6 = CLOCK CONFIGURATION (CC)
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge
(Default)
RCR.5-4 = RESERVED FOR FUTURE ENHANCEMENTS (R)
These bits are reserved for future use. Set reserved bits to “0.”
RCR.3 = BURST WRAP (BW)
0 = Wrap bursts within burst length set by RCR.2-0
1 = Don’t wrap accesses within burst length set by
RCR.2-0.(Default)
See
Section 4.10.7
for information about the BURST WRAP
configuration.
RCR.2–0 = BURST LENGTH (BL2–0)
001 = 4 Word Burst
010 = 8 Word Burst
011 = Reserved for future use
111 = Continuous (Linear) Burst (Default)
In the asynchronous page mode, the burst length always
equals four words.
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相關代理商/技術參數(shù) |
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|---|---|
| GT28F320D18B120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM |
| GT28F320S3-100 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile⑩ MEMORY FAMILY |
| GT28F320S3-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
| GT28F320W18BC60 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel? Wireless Flash Memory |
| GT28F320W18BC80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel? Wireless Flash Memory |
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