28F320D18
2
Product Preview
Upon initial power up or return from reset, the device defaults to a standard asynchronous page-
mode read configuration. Writing to the read configuration register at any device address enables
both partitions’ synchronous burst reads. In synchronous burst mode, the CLK input increments an
internal burst address generator, synchronizes flash memory with the host CPU, and outputs data
every CLK cycle. A WAIT# output signal provides easy CPU-to-flash memory communication and
synchronization.
In addition to the enhanced architecture and interface, 1.8 Volt Dual-Plane Flash memory
incorporates technology that enables fast factory programming/erasing and low-power designs.
Specifically designed for low-voltage systems, 1.8 Volt Dual-Plane Flash memory supports read
operations at 1.8 V V
CC
and block erase and program operations at 1.8 V or 12 V V
PP
. The 12 V
V
PP
option renders the fastest program/erase performance that can increase factory throughput.
With the 1.8 V V
PP
option, V
CC
and V
PP
can be tied together for a simple, ultra low-power design.
In addition to the voltage flexibility, the dedicated V
PP
pin gives complete data protection when
V
PP
≤
V
PPLK
.
The device’s Command User Interface (CUI) is the system processor’s interface to 1.8 Volt Dual-
Plane Flash memory’s internal operation. Writing a valid command sequence to the CUI initiates
device Write State Machine (WSM) controlled automation that automatically executes the block-
erase and program algorithms and timings. The status register indicates the WSM’s state by
indicating block erase or program completion and status.
An industry-standard command sequence invokes block-erase and program automation. Each
block erase operation erases one block. Data is programmed in word increments. Erase suspend
allows system software to pause a block erase so it can read or program data in another block in the
same partition. Program suspend allows system software to suspend programming so it can read
from another location in the same partition. It is also possible to nest suspends as follows: suspend
erase in the first partition, start programming in the second partition, suspend programming in the
second partition and then read from the second partition.
1.8 Volt Dual-Plane Flash memory offers two low-power savings features: Automatic Power
Savings (APS) and standby mode. The device automatically enters APS mode following read cycle
completion. Standby mode is initiated when the system deselects the device by driving CE#
inactive. RST# also resets the device to read array mode, provides write protection, and clears the
status register. Combined, these two features significantly reduce power consumption.
2.0
Product Description
2.1
Ballouts
The Intel 1.8 Volt Dual-Plane Flash memory is available in a 60-ball (7 x 8 matrix with four
support balls) μBGA* CSP (Chip Scale Package) package with 0.75 mm ball pitch that is ideal for
board-constrained applications.
Figure 1, “60-Ball μBGA* Package Ballout” on page 4
shows the component ballout.
2.2
Ball Description
Figure 1, “Ball Descriptions” on page 3
describes ball usage.