參數(shù)資料
型號(hào): GT28F320D18B110
英文描述: x16 Flash EEPROM
中文描述: x16閃存EEPROM
文件頁(yè)數(shù): 60/83頁(yè)
文件大?。?/td> 836K
代理商: GT28F320D18B110
28F320D18
56
Product Preview
8.6
AC Read Characteristics
NOTES:
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Tested at worst case processor conditions.
3. Sampled, not 100% tested.
4. Applies only to subsequent synchronous reads.
5. OE# may be delayed up to t
ELQV–
t
GLQV
after the falling edge of CE# without impact to t
ELQV
.
#
Sym
Product
-110
-120
Unit
Parameter
()
Notes
Min
Max
Min
Max
Clock Specifications
R1
t
CLK
CLK period
25
25
ns
R2
t
CH
(t
CL
)
CLK high (Low) time
7.5
7.5
ns
R3
t
CHCL
(t
CLCH
)
CLK fall (Rise) time
5
5
ns
Synchronous Specifications
R4
t
AVCH
Address valid setup to CLK
9
9
ns
R5
t
VLCH
ADV# low setup to CLK
9
9
ns
R6
t
ELCH
CE# low setup to CLK
9
9
ns
R7
t
CHQV
CLK to output delay
20
25
ns
R8
t
CHQX
Output hold from CLK
2
5
5
ns
R9
t
CHAX
Address hold from CLK
3
10
10
ns
R10
t
CHTL
(t
CHTH
)
CLK to WAIT# delay
20
25
ns
R24
t
EHEL
CE# high between subsequent
synchronous reads
4
20
20
ns
Asynchronous Specifications
R11
t
AVVH
Address setup to ADV# high
10
10
ns
R12
t
ELVH
CE# low to ADV# going high
10
10
ns
R13
t
AVQV
Address to output delay
5
110
120
ns
R14
t
ELQV
CE# low to output delay
110
120
ns
R15
t
VLQV
ADV# low to output delay
110
120
ns
R16
t
VLVH
ADV# pulse width low
10
10
ns
R17
t
VHVL
ADV# pulse width high
10
10
ns
R18
t
VHAX
Address hold from ADV# high
9
9
ns
R19
t
APA
Page address access time
40
45
ns
R20
t
GLQV
OE# low to output delay
45
45
ns
R21
t
PHQV
RST# high to output delay
150
150
ns
R22
t
EHQZ
t
GHQZ
CE# or OE# high to output in
high z, whichever occurs first
3
25
35
ns
R23
t
OH
Output hold from first occurring
address, CE#, or OE# change
3
0
0
ns
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