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參數(shù)資料
| 型號(hào)： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 6/47頁 |
| 文件大?。?/td> | 754K |
| 代理商： | GS9064 |
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GENNUM CORPORATION
22208 - 0
6 of 47
G
1.2 PIN DESCRIPTIONS
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
1
CP_VDD
-
Power
Power supply connection for the charge pump. Connect to +3.3V DC
analog.
2
PDBUFF_GND
-
Power
Ground connection for the phase detector and serial digital input buffers.
Connect to analog GND.
3
PD_VDD
-
Power
Power supply connection for the phase detector. Connect to +1.8V DC
analog.
4
BUFF_VDD
-
Power
Power supply connection for the serial digital input buffers. Connect to
+1.8V DC analog.
5
CD1
Non
Synchronous
Input
STATUS SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI1 and DDI1
pins is considered valid.
When HIGH, the associated serial digital input signal is considered to be
invalid. In this case, the LOCKED signal is set LOW and all parallel outputs
are muted.
6,8
DDI1, DDI1
Analog
Input
Differential input pair for serial digital input 1.
7
TERM1
Analog
Input
Termination for serial digital input 1. AC couple to PDBUFF_GND.
9
DVB_ASI
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with SMPTE_BYPASS = LOW, the device
will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the decoding or word
alignment of received DVB-ASI data.
10
IP_SEL
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select DDI1 / DDI1 or DDI2 / DDI2 as the serial digital input signal,
and CD1 or CD2 as the carrier detect input signal.
When set HIGH, DDI1 / DDI1 is selected as the serial digital input and
CD1 is selected as the carrier detect input signal.
When set LOW, DDI2 / DDI2 serial digital input and CD2 carrier detect
input signal is selected.
11
NC
-
-
No Connect.
12
20bit/10bit
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the output data bus width in SMPTE or Data-Through
modes. This signal is ignored in DVB-ASI mode.
When set HIGH, the parallel output will be 20-bit demultiplexed data.
When set LOW, the parallel outputs will be 10-bit multiplexed data.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9064A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9064-CKDE3 | 制造商:Gennum Corporation 功能描述:Cable Equalizer 16-Pin SOIC |
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