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參數(shù)資料
| 型號： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 35/47頁 |
| 文件大?。?/td> | 754K |
| 代理商： | GS9064 |
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GENNUM CORPORATION
22208 - 0
35 of 47
G
3.10.5.1 Video Standard Error Detection
If a mismatch between the received SMPTE 352M packets
and the calculated video standard occurs, the GS9060 will
indicate a video standard error by setting the VD_STD_ERR
bit of the ERROR_STATUS register HIGH.
3.10.5.2 EDH CRC Error Detection
The GS9060 calculates Full Field (FF) and Active Picture
(AP) CRC words according to SMPTE RP165 in support of
Error Detection and Handling packets in SD signals.
These calculated CRC values are compared with the
received CRC values. If a mismatch is detected, the error is
flagged in the AP_CRC_ERR and/or FF_CRC_ERR bits of
the ERROR_STATUS register. These two flags are shared
between fields 1 and 2.
The AP_CRC_ERR bit will be set HIGH when an active
picture CRC mismatch has been detected in field 1 or 2.
The FF_CRC_ERR bit will be set HIGH when a full field CRC
mismatch has been detected in field 1 or 2.
EDH CRC errors will only be indicated when the device is
operating in SMPTE mode, and when the device has
correctly received EDH packets.
SMPTE RP165 specifies the calculation ranges and scope
of EDH data for standard 525 and 625 component digital
interfaces. The GS9060 will utilize these standard ranges by
default.
If the received video format does not correspond to 525 or
625 digital component video standards as determined by
the flywheel pixel and line counters, then one of two
schemes for determining the EDH calculation ranges will be
employed:
1. Ranges will be based on the line and pixel ranges
programmed by the host interface; or
2. In the absence of user-programmed calculation ranges,
ranges will be determined from the received TRS timing
information.
The registers available to the host interface for
programming EDH calculation ranges include active picture
and full field line start and end positions for both fields.
Table 12 shows the relevant registers, which default to '0'
after device reset.
If any or all of these register values are zero, then the EDH
CRC calculation ranges will be determined from the
flywheel generated H signal. The first active and full field
pixel will always be the first pixel after the SAV TRS code
word. The last active and full field pixel will always be the
last pixel before the start of the EAV TRS code words.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9064A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9064-CKDE3 | 制造商:Gennum Corporation 功能描述:Cable Equalizer 16-Pin SOIC |
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