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參數(shù)資料
| 型號： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 21/47頁 |
| 文件大?。?/td> | 754K |
| 代理商： | GS9064 |
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GENNUM CORPORATION
22208 - 0
21 of 47
G
3. DETAILED DESCRIPTION
3.1 FUNCTIONAL OVERVIEW
The GS9060 is a dual-standard reclocking deserializer with
an integrated serial digital loop-through output. When used
in conjunction with any Gennum cable equalizer and the
external GO1525 Voltage Controlled Oscillator, a receive
solution at 270Mb/s is realized.
The application layer must set external device pins for the
correct reception of either SMPTE or DVB-ASI data. The
GS9060 also supports the reclocking and deserializing of
data not conforming to SMPTE or DVB-ASI streams.
The provided serial loop-through outputs may be selected
as either buffered or reclocked versions of the input signal
and feature a high impedance mode, output mute on loss of
signal and adjustable signal swing.
In the digital signal processing core, several data
processing functions are implemented including error
detection and correction and automatic video standards
detection. These features are all enabled by default, but
may be individually disabled via internal registers
accessible through the GSPI host interface.
Finally, the GS9060 contains a JTAG interface for boundary
scan test implementations.
3.2 SERIAL DIGITAL INPUT
The GS9060 contains two current mode differential serial
digital input buffers, allowing the device to be connected to
two SMPTE 259M-C compliant input signals.
Both input buffers have internal 50
termination resistors
which are connected to ground via the TERM1 and TERM2
pins. The input common mode level is set by internal
biasing resistors such that the serial digital input signals
must be AC coupled into the device. Gennum recommends
using a capacitor value of 4.7uF to accommodate
pathological signals.
The input buffers use a separate power supply of +1.8V DC
supplied via the BUFF_VDD and PDBUFF_GND pins.
3.2.1 Input Signal Selection
A 2x1 input multiplexer is provided to allow the application
layer to select between the two serial digital input streams
using a single external pin. When IP_SEL is set HIGH, serial
digital input 1 (DDI1 / DDI1) is selected as the input to the
GS9060's reclocker stage. When IP_SEL is set LOW, serial
digital input 2 (DDI2 / DDI2) is selected.
3.2.2 Carrier Detect Input
For each of the differential inputs, an associated carrier
detect input signal is included, (CD1 and CD2). These
signals are generated by Gennum's family of automatic
cable equalizers.
When LOW, CDx indicates that a valid serial digital data
stream is being delivered to the GS9060 by the equalizer.
When HIGH, the serial digital input to the device should be
considered invalid. If no equalizer preceeds the device, the
application layer should set CD1 and CD2 accordingly.
NOTE: If the GS9064 Automatic Cable Equalizer is used,
the MUTE/CD output signal from that device must be
translated to TTL levels before passing to the GS9060 CDx
inputs. See Section 4.1 for a recommended transistor
network that will set the correct voltage levels.
A 2x1 input multiplexer is also provided for these signals.
The internal carrier_detect signal is determined by the
setting of the IP_SEL pin and is used by the lock detect
block of the GS9060 to determine the lock status of the
device, (see Section 3.6).
3.2.3 Single Input Configuration
If the application requires a single differential input, the
second set of inputs may be left unconnected. Tie the
associated carrier detect pin HIGH, and leave the
termination pin unconnected.
3.3 SERIAL DIGITAL RECLOCKER
The output of the 2x1 serial digital input multiplexer passes
to the GS9060's internal reclocker stage. The function of
this block is to lock to the input data stream, extract a clean
clock, and retime the serial digital data to remove high
frequency jitter.
The reclocker was designed with a 'hexabang' phase and
frequency detector. That is, the PFD used can identify six
'degrees' of phase / frequency misalignment between the
input data stream and the clock signal provided by the
VCO, and correspondingly signal the charge pump to
produce six different control voltages. This results in fast
and accurate locking of the PLL to the data stream.
If lock is achieved, the reclocker provides an internal
pll_lock signal to the lock detect block of the device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| GS9064A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9064-CKDE3 | 制造商:Gennum Corporation 功能描述:Cable Equalizer 16-Pin SOIC |
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