- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370391 > GS9064 Telecomm/Datacomm PDF資料下載
參數(shù)資料
| 型號： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 23/47頁 |
| 文件大小： | 754K |
| 代理商： | GS9064 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
GENNUM CORPORATION
22208 - 0
23 of 47
G
3.5 SERIAL-TO-PARALLEL CONVERSION
The retimed data and phase-locked clock signals from the
reclocker are fed to the serial-to-parallel converter. The
function of this block is to extract 10-bit data words from the
reclocked serial data stream and present them to the
SMPTE and DVB-ASI word alignment blocks simultaneously.
3.6 LOCK DETECT
The lock detect block controls the center frequency of the
integrated reclocker to ensure lock to the received serial
digital data stream is achieved, and indicates via the
LOCKED output pin that the device has detected the
appropriate sync words.
Lock detection is a continuous process, which begins at
device power up or after a system reset, and continues until
the device is powered down or held in reset.
The lock detection algorithm first determines if a valid serial
digital input signal has been presented to the device by
sampling the internal carrier_detect signal. As described in
Section 3.2.2, this signal will be LOW when a good serial
digital input signal has been detected.
If the carrier_detect signal is HIGH, the serial data into the
device is considered invalid, and the VCO frequency will be
set to the center of the pull range. The LOCKED pin will be
LOW and all outputs of the device except for the PCLK
output will be muted. Instead, the PCLK output frequency
will operate within +/-3% of the rates shown in Table 15 of
Section 3.11.5.
NOTE: When the device is operating in DVB-ASI mode, the
parallel outputs will not mute when the carrier_detect signal
is HIGH. The LOCKED signal will function normally.
If a valid input signal has been detected the lock algorithm
will enter a hunt phase where four attempts are made to
detect the presence of either SMPTE TRS sync words or
DVB-ASI sync words. The center frequency of the reclocker
will be 270Mb/s.
Assuming that a valid SMPTE or DVB-ASI signal has been
applied to the device, asynchronous lock times will be as
listed in AC Characteristics, (see Section 2.3)
NOTE: The PCLK output will continue to operate during the
lock detection process. The frequency may toggle will be
27MHz when the 20bit/10bit pin is set LOW, and 13.5MHz
when 20bit/10bit is set HIGH.
For SMPTE and DVB-ASI inputs, the lock detect block will
only assert the LOCKED output signal HIGH if (1) the
reclocker has locked to the input data stream as indicated
by the internal pll_lock signal, and (2) TRS or DVB-ASI sync
words have been correctly identified.
If after four attempts lock has not been achieved, the lock
detection algorithm will enter into PLL lock mode. In this
mode, the reclocker will attempt to lock to the input data
stream without detecting SMPTE TRS or DVB-ASI sync
words. This unassisted process can take up to 10ms to
achieve lock.
When reclocker lock as indicated by the internal pll_lock
signal is achieved in this mode, data will be passed directly
to the parallel outputs without any further processing taking
place and the LOCKED signal will be asserted HIGH if and
only if the SMPTE_BYPASS and DVB_ASI input pins are set
LOW.
3.6.1 Input Control Signals
The GS9060 contains three input control signals which
determine how the device locks to the input.
It is required that the application layer set the
SMPTE_BYPASS and DVB_ASI inputs to reflect the
appropriate input data format. If either is configured
incorrectly, the device will not lock to the input data stream,
and the DATA_ERROR pin will be set LOW.
The third input signal, RC_BYP, allows the application layer
to determine whether the serial digital loop-through output
will be a reclocked or buffered version of the input, (see
Section 3.4.2). Table 2 shows the required settings for
various input formats.
TABLE 2 INPUT CONTROL SIGNALS
FORMAT
PIN SETTINGS
SMPTE_BYPASS
DVB_ASI
SD SMPTE
HIGH
LOW
DVB-ASI
LOW
HIGH
NOT SMPTE OR
DVB-ASI*
LOW
LOW
*NOTE: See Section 3.9 for a complete description of Data-
Through mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GSA1 | Fuse |
| GSA1.25 | Fuse |
| GSA1.6 | Fuse |
| GSA10 | Fuse |
| GSA750 | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9064A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9064-CKDE3 | 制造商:Gennum Corporation 功能描述:Cable Equalizer 16-Pin SOIC |
發(fā)布緊急采購，3分鐘左右您將得到回復。