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參數(shù)資料
| 型號： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 38/47頁 |
| 文件大?。?/td> | 754K |
| 代理商： | GS9064 |
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GENNUM CORPORATION
22208 - 0
38 of 47
G
3.10.6.1 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE
register is set LOW, the GS9060 will remap all codes within
the active picture between the values of 3FCh and 3FFh to
3FBh. All codes within the active picture area between the
values of 000h and 003h will be re-mapped to 004h.
In addition, 8-bit TRS and ancillary data preambles will be
remapped to 10-bit values if this feature is enabled.
3.10.6.2 EDH CRC Error Correction
The GS9060 will generate and insert active picture and full
field CRC words into the EDH data packets received by the
device. This feature is only available in SD mode and is
enabled by setting the EDH_CRC_INS bit of the
IOPROC_DISABLE register LOW.
EDH CRC calculation ranges are described in Section
3.10.5.2.
NOTE: Although the GS9060 will modify and insert EDH
CRC words and EDH packet checksums, EDH error flags
will not be updated by the device.
3.10.6.3 Ancillary Data Checksum Error Correction
When ancillary data checksum error correction and
insertion is enabled, the GS9060 will generate and insert
ancillary data checksums for all ancillary data words by
default. Where user specified ancillary data has been
programmed into the device (see Section 3.10.2.1), only the
checksums for the programmed ancillary data types will be
corrected.
This feature is enabled when the ANC_CSUM_INS bit of the
IOPROC_DISABLE register is set LOW.
3.10.6.4 TRS Error Correction
When TRS error correction and insertion is enabled, the
GS9060 will generate and insert 10-bit TRS code words as
required.
TRS word generation will be performed in accordance with
the timing parameters generated by the flywheel to provide
an element of noise immunity. As a result, TRS correction
will only take place if the flywheel is enabled, (FW_EN/DIS =
HIGH).
In addition, the TRS_INS bit of the IOPROC_DISABLE
register must be set LOW.
3.10.7 EDH Flag Detection
As described in Section 3.10.5.2, the GS9060 can detect
EDH packets in the received data stream. The EDH flags for
ancillary data, active picture and full field areas are
extracted from the detected EDH packets and placed in the
EDH_FLAG register of the device (Table 14).
One set of flags is provided for both fields 1 and 2. Field 1
flag data will be overwritten by field 2 flag data.
The EDH_FLAG register may be read by the host interface
at any time during the received frame except on the lines
defined in SMPTE RP165 where these flags are updated.
NOTE 1: By programming the ANC_TYPE1 register (005h)
with the DID word for EDH ancillary packets, the application
layer may detect a high-to-low transition on either the YANC
or CANC output pin of the GS9060 to determine (a) when
EDH packets have been received by the device, and (b)
when the EDH_FLAG register can be read by the host
interface. See Section 3.10.2 for more information on
ancillary data detection and indication.
NOTE 2: The bits of the EDH_FLAG register are sticky and
will not be cleared by a read operation. If the GS9060 is
decoding a source containing EDH packets, where EDH
flags may be set, and the source is replaced by one without
EDH packets, the EDH_FLAG register will not be cleared.
NOTE 3: The GS9060 will detect EDH flags, but will not
update the flags if an EDH CRC error is detected.
Gennum's GS9062 Serializer allows the host to individually
set EDH flags.
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