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參數(shù)資料
| 型號(hào)： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 43/47頁 |
| 文件大?。?/td> | 754K |
| 代理商： | GS9064 |
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GENNUM CORPORATION
22208 - 0
43 of 47
G
3.13 JTAG
When the JTAG/HOST input pin of the GS9060 is set HIGH,
the host interface port will be configured for JTAG test
operation. In this mode, pins 27 through 30 become TMS,
TDO, TDI, and TCK. In addition, the RESET_TRST pin will
operate as the test reset pin.
Boundary scan testing using the JTAG interface will be
enabled in this mode.
There are two methods in which JTAG can be used on the
GS9060:
1. As a stand-alone JTAG interface to be used at in-circuit
ATE (Automatic Test Equipment) during PCB assembly;
or
2. Under control of the host for applications such as
system power on self tests.
When the JTAG tests are applied by ATE, care must be
taken to disable any other devices driving the digital I/O
pins. If the tests are to be applied only at ATE, this can be
accomplished with tri-state buffers used in conjunction with
the JTAG/HOST input signal. This is shown in Figure 19.
Figure 19 In-Circuit JTAG
Alternatively, if the test capabilities are to be used in the
system, the host may still cntrol the JTAG/HOST input
signal, but some means for tri-stating the host must exist in
order to use the interface at ATE. This is represented in
Figure 20.
Figure 20 System JTAG
Please contact your Gennum representative to obtain the
BSDL model for the GS9060.
3.14 DEVICE POWER UP
Because the GS9060 is designed to operate in a multi-volt
environment, any power up sequence is allowed. The
charge pump, phase detector, core logic, serial digital
input/output buffers and digital I/O buffers should all be
powered up within 1ms of one another.
Device pins may also be driven prior to power up without
causing damage.
To ensure that all internal registers are cleared upon power-
up, the application layer must hold the RESET_TRST signal
LOW for a minimum of 1ms after the core power supply has
reached the minimum level specified in the DC Electrical
Characteristics Table (see Section 2.2). See Figure 21.
3.15 DEVICE RESET
In order to initialize all internal operating conditions to their
default states the application layer must hold the
RESET_TRST signal LOW for a minimum of t
reset
= 1ms.
When held in reset, all device outputs will be driven to a
high-impedance state.
Figure 21 Reset Pulse
Application HOST
GS9060
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
In-circuit ATE probe
Application HOST
GS9060
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
In-circuit ATE probe
Tri-State
CORE_VDD
RESET_TRST
t
reset
+1.65V
+1.8V
Reset
Reset
t
reset
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